Gate Resistance Influence on Integrated Circuits in MESFET Technology
IntroductionThe aim of this work is the study of the logical integrated circuits based gallium arsenide gate Schottky field-effect transistors called GaAs MESFET. As a matter of fact, the integrated circuits development has a very important impact on the whole of electronics effectively, since 1961 dates from the first integrated circuit, to 1971 that saw the first microprocessor apparition, the micro electronics passed from to LSI circuits with thousand of integrated components and now to circuits VLSI circuits integrating several hundreds of thousands of devices. In this study, we are first interested by the gallium arsenide GaAs material that is the bases of this technological evolution, then to different structures of MESFET GaAs component which composes a choice device for the conception and the realization of ultra fast logic circuits at propagation time inferior to the nanosecond.
Our survey consists in improving the component's performance: to have a low noise by reducing the gate length, minimizing the parasitic' sources and reducing the gate resistances. We will study, at a given frequency, the noise variations respectively according to the channel length and width. We will also study particularly the capacitive effect of the resistance Rg at microwave and millimetre –length wave frequencies
1. GaAs material: The choice of GaAs as material permitting to obtain very high performances for the integrated circuits is not only related to very interesting semi- conducting properties but to a propitious compromise between different criterion such as the metallurgic properties, ability to technological realisation ,working temperature, tolerance to radiations. The last year technological progress permitted GaAs and its ternary derivatives to be the second generation material.
1.1. Transport properties: The N type gallium arsenide presents excellent transport properties . For weak values of the doping of material doping, mobility at weak field can reach values of 8000-9000 cm2/Vs at the ambient temperature (10000 to 80000 cm2/Vs with 77 ° K). At the usual doping (1017 .Cm-3), the electrons mobility is six times higher in GaAs than in the Si and their transport speed is twice (higher) faster. The speed saturation at high electric field is reached for an electric field less higher than the Si. As a result ,the transit time of GaAs MESFET with gate length between 0.5 and 0.1 μm is of the order of 10 to 20 picoseconds corresponding to cut-off frequencies of gain the product incurrent - pass bandbetween 20 to 30 GHz. For a similar conception, we point out merit factor for to six times superior to those obtained on silicon JFET devices.
1.2. Electric Properties: The electric properties of GaAs with 300 °K intervening in the discrete or integrated circuits manufacture are gathered in table 1.
1.3. Semi-insulating substrate: The semi insulating GaAs material availability (resistivity included between l0^7 and l0^9 cm with T=300°K°) is a substantial advantage from technological and electrical performance point of view. The inter device insulation is ensured without circuits performances damage: thus the parasitic capacities linked to the mass plan remain inferior to the coplanar parasitic capacities of drain- source contacts interconnections lines. The obtaining method of semi-insulating GaAs substrates consists in compensating the residual levels obtained materials using the of Bridgman method by a specifically deep impurity; the chrome being mostly used. The use of ionic implantation of the chrome doped GaAs obtained by Bridgman growth revealed anomalies appearing during the annealing after implantation. The phenomenon tied to the Cr oxodiffusion during the thermal treatment is identical to the one met on epitaxied layers on Cr doped GaAs.
2. GaAs MESFET transistors manufacture On GaAs, the base component is in fact the Schottky gate field-effect transistor called MESFET (Metal Semiconductor Field Effect- Transistor) which is a majority carriers device, its structure is particularly simple easily realizable in N type thin layer. This MESFET active layer is a thin conducting uniform layer with a thickness d (1000-2000) with can vary doping between 1016 and 3.1017 Cm-3 according to the structure, N doped by means of sulphur or tin some time . The active layer growth is realized by various technologies:
- Liquid phase epitaxy, the later does not allow a strict control thickness d.
- molecular jets epitaxy that allows an excellent control of active layer thickness(a few thousands of Angströms – layer ) and is particularly well adapted to the GaAs MESFET realization ,of normally blocked said Normally OFF.
- Ionic implantation, this semi isolating doping technique permits to realise layers with properties similar to those obtained by epitaxy and present certain advantages for the reproducibility and structure homogeneity.
- Vapor phase epitaxy by metallic device or chlorids is the softest method and the most adapted to the industrial treatment; it actually remains the privileged toolt for the discrete devices.
The N layer region (figure 1-a) form the active area. The source -drain contact are composed by an "eutectique "obtained by an alloy (400-500°C) of thr gold germanium layer with GaAs. Metallization of nearly 0.5 μm thicknesses formed by a titanium gold compo doposit ensure the device interconnections with the elements. The MESFET main advantage is the particularly simple gate structure that always to reduce its geometry to extreme values comparatively to other transistors. It is sufficient to engrave on GaAs the metallic band that forms the grate. For the integrated circuits, the typical length is of 1μm but the actual tendency is to pass to the submicronics geometries. the gate length which determines at the time the input capacity on the electrons transit time in the channel conditions the performances at average velocity of 107 cm.s-1, leads to a 10 ps a transit time and a current gain cut-off frequency of the order of 15 GHz. Taking the new possibilities in micro lithography into consideration, the microelectronics on GaAs is more advanced than silicon technology.
2.1. Structure with and without buffer layer The first transistor as being realised by means of epitaxial layers directly deposited on semi –insulating substrate (figure 1-a)
Their performances have being affected by effects by hysteresis. Is effect in order to minimize the activate substrate interface layer, it has became classical to insert an epitaxial layer called "buffer" weakly doped (1012 to 1011 cm-3 ) and which the average thickness is of 1the order 10 μm (figure 1 - b). In order to improve the device performances, several manufacture techniques has being proposed .We will present some of them.
2.2. Ploughed or buried gate GaAs MESFET" In GaAs and for a free face, there is potential barrier near the surface one (figure 2). This latter is expressed by the space charge density existence, extending in the drain gate and source gate - space.
It follows a noticeable increase in access resistances. The latter limit the current which is then badly controlled by the gate (particularly for the weak gate polarization or lightly positive) . To improve the transistor command, we realise a buried gate. This structure is realised by grooving using by a chemic attack or plasma engraving, a trench in the semiconductor between the source and drain contacts. Then the gate metal is pulverized at the very bottom of this trench. By this method we reduce the access resistances to the intrinsic region of the component (under the gate) due the lateral region uncontrolled by the gate. This process presents, however, the disadvantage to increase the technological operations complexity .we often prefers the locad ionic implantation technics that permit to over dope the inter electrode regions and consequently to decrease the access resistances by selectively increasing the donors density Nd (N type semiconductor N type) under the lateral regions.
2.3. Buffer layer structure GaAs MESFET To improve the GaAs MESFET commutation and hyper frequency performances many gate configuration are considered figure (3-a) shows a structure with semi insulating gate, manufactured by Ar bombing of the gate region. The device can reduce the capacity, reduce also gate the leakage current and increase the tension of breakdown voltage. The figure (3-b) shows a similar structure with a gate in "buffer". This layer is inserted between the gate metal and the active layer, the self-aligning technics has being used to realised components with submicronic gate length.
3. Equivalent circuit of the MESFET The equivalent circuit of a component MMIC must sufficiently represent all the important physical characteristics of the device and exploit the relationship between the equivalent elements of the circuit and physique of the device which will be useful in the mathematical formulation. Transistor MESFET and HEMT to study is represented on figure 5-a. the structure which determines the behaviour of microwave of a transistor MESFET is identified on the figure 5-b; some of parameters important are deferred in.
To distinguish this well-known resistance from the component MESFET which is the aim of this article, we presented this access resistance along the gate finger rga ,it is then the end to end normal metallization resistance given by:
where the frequency characteristic for the beginning of the significant skin effect is:
μo = 4.10-7 Vs/Am is the free space permeability, and a geometrical factor, roughly equal to 3,5 for a cross section of the cross-section. For a rga=150 Ω/mm, the fse is 420 GHz. Although can be reduced by the presence of a plane on the ground, the skin effect seems certainly to be negligible. We prove numerically that the skin effect is indeed negligible, and that eqns. (3) - (4) are precise and adapted for SBGMESFET. Another resistive component on the input side of the MESFET is the filling resistance Ri (or Rgs) for the gate - source capacity. This parameter is often hard to separate from Rg during the extraction of the equivalent circuit. However, Ri is between a sixth and a fifth of the channel resistance for a used zero-drain-polarization.
Where Ro is the plate resistance and Idmax the current saturation of the channel, vsat is the speed of saturation, and μ the mobility. The factor 1/5 in eqn. (5) is the higher limit of quantity:
Where Rij and Iij parameters determine the Y parameters, and are derived from the waves linear equation of the MESFET inside. It explains both the distributed nature of Ri, and the change of the electron concentration of the sheet along the channel. Both eqns. (1) and (5) foresee very small resistances, often much smaller than the values produced by methods of extraction of equivalent circuit. It is an indication of an additional component in the input resistance, whose physics must be established in order to understand better the MESFET component, and to produce measurable models. To finish the study of effect of the conducting semi metal interface, we add a component to Rg resistance which defines the gate resistance f the normalized interfacial resistance. This resistance is defined as a contact resistance with the substrate, rgi being the normal gate resistance of the normalized interfacial resistance.
Simulation AC of the influence of the gate resistance and gate length on the input and output impedance of GaAs MESFET transistors are represented on figures 6, 7 and 8.
5. Influence of the gate on the noise factor We can observe three different sources of noise: For low frequencies the factor (1/F) called wavering noise which draws its performance from the low frequency and the care should be taken to avoid excessive attenuation of the signal compared to the signal at lower frequencies; this noise will not be important in amplifiers which operate above the frequency (which is the frequency that the thermal noise starts to dominate this noise) .This noise causes a serious problem in the oscillators and the mixers because of the non -linearity intrinsic devices . This noise is primarily due to carriers hopping in and out of deep levels in the substrate, buffer, and active layer and out of surface traps on the channel surfaces. It can be minimized by the deep –level density control and by the passivation of active layer surfaces. For this reason, HBT and HEMT appear essentially to be of better candidates for these applications with great controls and qualities which are now available with the epitaxial growth techniques. At larger frequencies parasitic resistances such as RS and RG starts to dominate the sources of disturbance of the device. We should add to this the noise created by the thermally induced statistic fluctuation in the local carrier density in the channel. The principal application of GaAs MESFET was in amplification with weak noise. It is important in the determination of a simple analytical expression to calculate the factor of minimum noise of a field-effect transistor. Since the factor of noise of a field-effect transistor is carried out by taking into account the point of operation and the equivalent impedance of the circuit. The noise factor: NF is related to four elements: gmo, Cgc RS and Rg which are measured starting from the S parameters extracted empirically from small model signal, Fukui derived a simple expression for NF:
Or the factor KF = 2.5 to 3.0 transistors MESFET and KF =1.5 to 2.0 for HEMT. Factor KF is often a simplification of noise generated by the drain current. Another simple expression of the noise was defined by Delagebeaudeuf and Al;
The simulation of the noise factor is shown on the figure 9 shows that we must reduce the gate length and minimize the parasitic source of the gate resistances. At a given frequency, the noise factor decreases with the channel length; it also decreases with the channel width; as a consequence of the reduction of RG for narrower gate. It is also proved that a field-effect transistor uniformly doped yields less noise than the other devices which have the same geometry. This result is due to the reduction of gm (but not gm/CGS) for MESFET transistors.
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