3. Transit Time Microwave Devices
There are several types of active two-terminal diodes that can oscillate or supply gain at microwave and millimeter-wave frequencies. These devices can be fabricated from a variety of semiconductor materials, but Si, GaAs, and InP are generally used. The most common types of active diodes are the IMPATT (an acronym for IMPact Avalanche Transit-Time) diode, and the Transferred Electron Device (generally called a Gunn diode). Tunnel diodes are also capable of producing active characteristics at microwave and millimeter-wave frequencies, but have been replaced in most applications by three-terminal transistors (such as GaAs MESFETs and AlGaAs/GaAs HEMTs), which have superior RF and noise performance, and are also much easier to use in systems applications. The IMPATT and Gunn diodes make use of a combination of internal feedback mechanisms and transit-time effects to create a phase delay between the RF current and voltage that is more than 90°, thereby generating active characteristics. These devices have high frequency capability since the saturated velocity of an electron in a semiconductor is high (generally on the order of ~107 cm/sec) and the transit time is short since the length of the region over which the electron transits can be made on the order of a micron (i.e., 10–4 cm) or less. The ability to fabricate devices with layer thicknesses on this scale permits these devices to operate at frequencies well into the millimeter-wave region. Oscillation frequency on the order of 400 GHz has been achieved with IMPATT diodes, and Gunn devices have produced oscillations up to about 150 GHz. These devices have been in practical use since the 1960s and their availability enabled a wide variety of solid-state system components to be designed and fabricated.
Semiconductor Material Properties
Active device operation is strongly dependent upon the charge transport, thermal, electronic breakdown, and mechanical characteristics of the semiconductor material from which the device is fabricated. The charge transport properties describe the ease with which free charge can flow through the material. This is described by the charge velocity-electric field characteristic, as shown in Fig. 3.1 for several commonly used semiconductors. At low values of electric field, the charge transport is ohmic and the charge velocity is directly proportional to the magnitude of the electric field. The proportionality constant is called the
mobility and has units of cm2/V-sec. Above a critical value for the electric field, the charge velocity (units of cm/sec) saturates and either becomes constant (e.g., Si) or decreases with increasing field (e.g., GaAs). Both of these behaviors have implications for device fabrication, especially for devices intended for high frequency operation. Generally, for transit time devices, a high velocity is desired since current is directly proportional to velocity. The greatest saturated velocity is demonstrated for electrons in the wide bandgap semiconductors, SiC and GaN. Both of these materials have saturated electron velocities on the order of vs ~ 2×107 cm/sec. This is one of the main reasons these materials are being developed for high frequency electronic devices. Also, a low value for the magnitude of the electric field at which velocity saturation occurs is desirable since this implies high charge mobility. High mobility produces low resistivity, and therefore low values for parasitic and access resistances for semiconductor devices. The decreasing electron velocity with electric field characteristic for compound semiconductors such as GaAs and InP makes active two-terminal devices called Transferred Electron Devices (TED's) or Gunn diodes possible. The negative slope of the velocity versus electric field characteristic implies a decreasing current with increasing voltage. That is, the device has a negative resistance. When a properly sized piece of these materials is biased in the region of decreasing current with voltage, and placed in a resonant cavity, the device will be unstable up to very high frequencies. By proper selection of embedding impedances, oscillators or amplifiers can be constructed.
Other semiconductor material parameters of interest include thermal conductivity, dielectric constant, energy bandgap, electric breakdown critical field, and minority carrier lifetime. The thermal conductivity of the material is important because it describes how easily heat can be extracted from the device. The thermal conductivity has units of W/cm-°K, and in general, high thermal conductivity is desirable. Compound semiconductors, such as GaAs and InP, have relatively poor thermal conductivity compared to elemental semiconductors such as Si. Materials such as SiC have excellent thermal conductivity and are used in high power electronic devices. The dielectric constant is important since it represents capacitive loading and, therefore, affects the size of the semiconductor device. Low values of dielectric constant are desirable since this permits larger device area, which in turn results in increased RF current and increased RF power that can be developed. Electric breakdown characteristics are important since electronic breakdown limits the magnitudes of the DC and RF voltages that can be applied to the device. A low magnitude for electric field breakdown limits the DC bias that can be applied to a device, and thereby limits the RF power that can be handled or generated by the device. The electric breakdown for the material is generally described by the critical value of electric field that produces avalanche ionization. Minority carrier lifetime is important for bipolar devices, such as pn junction diodes, rectifiers, and bipolar junction transistors (BJTs). A low value for minority carrier lifetime is desirable for devices such
as diode temperature sensors and switches where low reverse bias leakage current is desirable. A long minority carrier lifetime is desirable for devices such as bipolar transistors. For materials such as Si and SiC the minority carrier lifetime can be varied by controlled impurity doping. A comparison of some of the important material parameters for several common semiconductors is presented in Table 3.1. The large variation for minority lifetime shown in Table 3.1 for SiC and GaN is due to relatively immature materials growth technology for these wide bandgap semiconductors.
Two-Terminal Active Microwave Devices
The IMPATT diode, transferred electron device (often called a Gunn diode), and tunnel diode are the most commonly used two-terminal active devices. These devices can operate from the low microwave through high mm-wave frequencies, extending to several hundred GHz. They were the first semiconductor devices that could provide useful RF power levels at microwave and mm-wave frequencies and were extensively used in early systems as solid-state replacements for vacuum tubes. The three devices are similar in that they are fabricated from diode or diode-like semiconductor structures. DC bias is applied through two metal contacts that form the anode and cathode electrodes. The same electrodes are used for both the DC and RF ports and since only two electrodes are available, the devices must be operated as a one-port RF network, as shown in Fig. 3.2. This causes little difficulty for oscillator circuits, but is problematic for amplifiers since a means of separating the input RF signal from the output RF signal must be devised. The use of a nonreciprocal device, such as a circulator can be used to accomplish the task. Circulators, however, are large, bulky, and their performance is sensitive to thermal variations. In general, circulators are difficult to use for integrated circuit applications. The one-port character of diodes has limited their use in modern microwave systems, particularly for amplifiers, since transistors, which have three terminals and are two-port networks, can be designed to operate with comparable RF performance, and are much easier to integrate. Diodes, however, are often used in oscillator circuits since these components are by nature one-port networks. IMPATT and Gunn diodes require a combination of charge injection and transit time effects to generate active characteristics and they operate as negative immittance components (the term "immittance" is a general reference that includes both "impedance" and "admittance"). When properly designed and biased,
the active characteristics of the diodes can be described as either a negative resistance or a negative conductance. Which description to use is determined by the physical operating principles of the particular device, and the two descriptions are, in general, not interchangeable. Bias and RF circuits for the two active characteristics must satisfy different stability and impedance matching criteria. Transit time effects alone cannot generate active characteristics. This is illustrated in Fig. 3.3, which shows a general impedance plane. All passive circuits, no matter how complex or how many circuit elements are included, when arranged into a one-port network as shown in Fig. 3.2, and viewed from an external vantage point, will have an input impedance that lies in the right-hand plane of Fig. 3.3. The network resistance will be positive and real, and the reactance will be inductive or capacitive. This type of network is not capable of active performance and cannot add energy to a signal. Transit time effects can only produce terminal impedances with inductive or capacitive reactive effects, depending upon the magnitude of the delay relative to the RF period of the signal. In order to generate active characteristics it is necessary to develop an additional delay that will result in a phase delay between the terminal RF voltage and current that is greater than 90° and less than 270°. The additional delay can be generated by feedback that can be developed by physical phenomena internal to the device structure, or created by circuit design external to the device. The IMPATT and Gunn diodes make use of internal feedback resulting from electronic charge transfer within the semiconductor structure. The internal feedback generally produces a phase delay of ~90°, which when added to the transit time delay will produce a negative real component to the terminal immittance.
Tunnel Diodes
Tunnel diodes generate active characteristics by an internal feedback mechanism involving the physical tunneling of electrons between energy bands in highly doped semiconductors, as illustrated in the energy band diagram shown in Fig. 3.4. The illustration shows a p+n junction diode with heavily doped conduction and valence bands located in close proximity. When a bias is applied, charge carriers can tunnel through the electrostatic barrier separating the p-type and n-type regions, rather than be thermionically emitted over the barrier, as generally occurs in most diodes. When the diode is biased (either forward or reverse bias) current immediately flows and ohmic conduction characteristics are obtained. In the forward bias direction conduction occurs until the applied bias forces the conduction and valence bands
to separate. The tunnel current then decreases and normal, thermionic junction conduction occurs. In the forward bias region where the tunnel current is decreasing with increasing bias voltage an N-type negative immittance characteristic is generated, as shown in Fig. 3.5a. The immittance is called "N-type" because the I-V characteristic looks like the letter N. This type of active element is current driven and is short-circuit stable. It is described by a negative conductance in shunt with a capacitance, as shown in Fig. 3.5b. Tunnel diodes are limited in operation frequency by the time it takes for charge carriers to tunnel through the junction. Since this time is very short (on the order of 10 –12 s) operation frequency can be very high, approaching 1000 GHz. Tunnel diodes have been operated at 100s of GHz, and are primarily limited in frequency response by practical packaging and parasitic impedance considerations. The RF power available from a tunnel diode is limited (~100s of mW level) since the maximum RF voltage swing that can be developed across the junction is limited by the forward turn-on characteristics of the device (typically 0.6 to 0.9 v). Increased RF power can only be obtained by increasing device area to increase RF current. However, increases in diode area will limit operation frequency due to increased diode capacitance. Tunnel diodes have moderate DC-to-RF conversion efficiency (<10%) and very low noise figures and have been used in low noise systems applications, such as microwave and mm-wave receivers used for radioastronomy.
Transferred Electron Devices
Transferred electron devices (i.e., Gunn diodes) also have N-type active characteristics and can be modeled as a negative conductance in parallel with a capacitance, as shown in Fig. 3.5b. Device operation, however, is based upon a fundamentally different principle. The negative conductance derives from the complex conduction band structure of certain compound semiconductors, such as GaAs and InP. In these direct bandgap materials the lower valley central (or Γ) conduction band is in close energymomentum proximity to secondary, higher order conduction bands (i.e., the X and L) valleys (illustrated schematically as the L upper valley in Fig. 3.6). The electron effective mass is determined by the shape of the conduction bands and the effective mass is "light" in the Γ valley, but "heavy" in the higher order X and L upper valleys. When the crystal is biased, current flow is initially due to electrons in the light effective mass Γ valley and conduction is ohmic. However, as the bias field is increased, an increasing proportion of the free electrons are transferred into the X and L valleys where the electrons have heavier effective mass. The increased effective mass slows down the electrons, with a corresponding decrease in conduction current through the crystal. The net result is that the crystal displays a region of applied bias
voltages where current decreases with increasing voltage. That is, a negative resistance is generated. A charge dipole domain is formed in the device, and this domain will travel through the device generating a transit time effect. The combination of the transferred electron effect and the transit time delay will produce a phase shift between the terminal RF current and voltage that is greater than 90°. The device is unstable and when placed in an RF circuit or resonant cavity, oscillators or amplifiers can be fabricated. The Gunn device is not actually a diode since no pn or Schottky junction is used. The transferred electron phenomenon is a characteristic of the bulk material and the special structure of the conduction bands in certain compound semiconductors. In order to generate a transferred electron effect, a semiconductor must have Γ, X, and L valleys in the conduction bands in close proximity so that charge can be transferred from the lower Γ valley to the upper valleys at reasonable magnitude of applied electric field. It is desirable that the charge transfer occur at low values of applied bias voltage in order for the device to operate with good DC-to-RF conversion efficiency. Most semiconductors do not have the conduction band structure necessary for the transferred electron effect, and in practical use, Gunn diodes have only been fabricated from GaAs and InP. It should be noted that the name "Gunn diode" is actually a misnomer since the device is not actually a diode, but rather a piece of bulk semiconductor. TEDs are widely used in oscillators from the microwave through high mm-wave frequency bands.
They can be fabricated at low cost and provide an excellent price-to-performance ratio. They are, for example, the most common oscillator device used in police automotive radars. They have good RF output power capability (mW to W level), moderate efficiency (< 20%), and excellent noise and bandwidth capability. Octave or multi-octave band tunable oscillators are easily fabricated using devices such as YIG (yttrium iron garnet) resonators. High tuning speed can be achieved by using varactors as the tuning element. Many commercially available solid-state sources for 60 to 100 GHz operation (for example, automotive collision-avoidance radars) often use InP TEDs.
IMPATT Diodes
IMPATT (IMPact Avalanche Transit Time) diodes are fabricated from pn or Schottky junctions. The doping profile in the device is generally tailored for optimum performance and a typical p+nn+junction device structure as shown in Fig. 3.7. The diode is designed so that when it is reverse biased, the n-region is depleted of free electrons. The electric field at the p+n junction exceeds the critical magnitude for avalanche breakdown, and the electric field exceeds the magnitude required to maintain electron velocity saturation throughout the n-region. Saturated charge carrier velocity must be maintained throughout the RF cycle in order for the device to operate with maximum efficiency. In operation, the high electric field region at the p+n interface will generate charge when the sum of the RF and DC bias voltage produces an electric field that exceeds the critical value. A pulse of free charge (electrons and holes) will be generated. The holes will be swept into the p+region and the electrons will be injected into the depleted n-region, where they will drift through the diode, inducing a current in the external circuit as shown in Fig. 3.8. Due to the avalanche process, the RF current across the avalanche region lags the RF voltage by 90°. This inductive delay is not sufficient, by itself, to produce active characteristics. However, when the 90° phase shift is added to that arising from an additional inductive delay caused by the transit time of the carriers drifting through the remainder of the diode external to the avalanche region, a phase shift between the terminal RF voltage and current greater than 90° is obtained. A Fourier analysis of the resulting waveforms reveals a device impedance with a negative real part. That is, the device is active and can be used to generate or amplify RF signals. The device impedance has an "S-type" active i-v characteristic, as shown in Fig. 3.9a, and the device equivalent circuit consists of a negative resistance in series with an inductor, as shown in Fig. 3.9b. An S-Type active device is voltage driven and is open-circuit stable. For IMPATT diodes, the active characteristics only exist under RF conditions. That is, there is a lower frequency below which the diode does not generate a negative resistance. Also, the negative resistance is generally small in magnitude, and on the order of –1Ω to –10Ω. Therefore, it is necessary to reduce all parasitic resistances in external circuits to the maximum extent possible since parasitic series
resistance will degrade the device's negative resistance, thereby limiting device performance. An IMPATT diode has significant pn junction capacitance that must be considered and a complete equivalent circuit includes the device capacitance in parallel with the series negative resistance-inductance elements, as shown in Fig. 3.9b. For optimum performance the drift region is designed so that the electric field throughout the RF cycle is sufficiently high to produce velocity saturation for the charge carriers. In order to achieve this it is common to design complex structures consisting of alternating layers of highly doped and lightly doped semiconductor regions. These structures are called "high-low," "low-high-low," or "Read" diodes, after the man who first proposed their use. They can also be fabricated in a back-to-back arrangement to form double-drift structures. These devices are particularly attractive for mm-wave applications since the back-to-back arrangement permits the device to generate RF power from series-connected diodes, but each diode acts independently with regard to frequency response.
IMPATT diodes can be fabricated from most semiconductors, but are generally fabricated from Si or GaAs. The devices are capable of good RF output power (mW to tens of W) and good DC-to-RF conversion efficiency (~10 to 20%). They operate well into the mm-wave region and have been operated at frequencies in excess of 400 GHz. They have moderate bandwidth capability, but have relatively poor noise performance due to the impact ionization process associated with avalanche breakdown. The powerfrequency performance of IMPATT diodes fabricated from Si, GaAs, and SiC is shown in Fig. 3.10. The Si and GaAs data are experimental, and the SiC data are predicted from simulation. The numbers associated with the data points are the conversion efficiencies for each point.
Within a few years of the discovery of the transistor, its theory of operation was developed and refined. The decade of the 1950s was a race toward the development of a practical technique to fabricate them. Research into various aspects of the material sciences led to the development of the planar process with silicon as the cornerstone element. Substrate and epitaxial growth, dopant diffusion, ion-implantation, metalization, lithography, and oxidation had to be perfected and integrated into a manufacturable process flow. These efforts culminated with Robert Noyce's patent application for the planar silicon BJT IC concept that he invented while at Fairchild. In the 1960s, the first commercial ICs appeared on the market, launching the modern age of electronics. Since then, transistor performance and integration levels have skyrocketed driven primarily by advances in materials, metrology, and process technology as well as competition, cost, and opportunity.
where Is is called the saturation current and Vt is Boltzmann's thermal voltage kT/q, which is 26 mV at room temperature (RT). This expression plotted in Fig. 4.1b is valid over many decades of current and its implications are far reaching in BJT IC design. Consider the small-signal transfer characteristics relating the output current to input voltage at a given bias current, Ic , i.e., the transconductance, gm. It is given by the remarkably simple expression,
(4.2)
The notion that transconductance is precisely and linearly proportional to the bias current, Ic and inversely proportional to temperature through Vt is known as translinearity. Notice that Is, which has a strong dependence on temperature, base-width, and other physical device parameters, has dropped out of the picture. This view of bipolar transistors as a voltage-controlled current source suggests that it should have been named the transductor rather than the transistor. Although bipolar transistors are usually considered hopelessly nonlinear because of the exponential law in Eq. (4.1), extremely precise and robust linear and nonlinear functions can be realized at very high frequencies by proper circuit techniques that exploit the translinear property embodied in Eq. (4.2). The intrinsic bandwidth of high frequency BJTs is ultimately limited by minority carrier storage primarily in the base region. Current is conveyed from the emitter to the collector by the relatively slow process of diffusion resulting from the gradient in the distribution of stored minority carriers in the base. In contrast, current in FETs is transported by the faster process of majority carrier drift in response to
an electric field. By invoking the quasi-static approximation, which assumes that signals of interest change on a much longer time scale than the device time constants, carrier storage can be modeled as a lumped diffusion capacitance, Cd given by,
(4.3)
where Qd is the stored charge and τf is the forward transit time. The parameter τf can be viewed as the average time an electron spends diffusing across the base and can be expressed as a function of basic material and device parameters,
(4.4)
where WB is the physical base width, Dn is the electron diffusion coefficient, and η is a dimensionless factor that accounts for any aiding fields in the base. Despite the limitations associated with carrier storage and diffusion, BJTs have demonstrated excellent high frequency performance. This is partly due to their vertical nature where dimensions such as WB can be significantly less than 100 nm. In contrast, FETs are laterally arranged devices where the critical dimension through which carriers drift is determined by lithography and is typically larger than 100 nm even in the most advanced technologies. Furthermore, the fundamental limit contained in τf is never achieved in practice since other factors, both device and circuit-related, conspire to reduce the actual bandwidth.
A first order model of BJTs is illustrated in Fig. 4.2 consisting of a diode at the base-emitter junction whose current is conveyed entirely to the collector according to Eq. (4.1) and a diffusion capacitance that models the carrier storage. From this simplistic model, the transistor ft, defined as the frequency at whichthe common-emitter short-circuit current gain, h21, reaches unity, can be calculated from,
(4.5a)
(4.5b)
Note that ft is independent of current and is solely a function of material parameters and device design details. Pushing this figure of merit to higher frequencies has dominated industrial and academic research for years. Polysilicon emitter BJTs, Si/SiGe heterojunction BJTs (HBTs), and III-V-based HBTs are all attempts to craft the active layers in order to maximize ft without significantly compromising other device aspects.
Parasitics and Refinements
The first order model captures the essential operation of the BJT. However, actual devices deviate from that ideal in many aspects. As electrons diffuse across the base, some are lost to the process of recombination with holes as illustrated in Fig. 4.3a. Excess holes are also parasitically injected into the emitter.
This overall loss of holes must originate at the base terminal and represents a finite base current, Ib, which is related to Ic via the parameter, β, known as the common emitter current gain,
(4.6)
The effect of finite β is to modify the emitter-base diode current by a correction factor, α, known as the common-base current gain, that accounts for the extra base current. Since Ie= Ib + Ic, it is easy to show that,
(4.7)
so that the emitter-base diode current now becomes Is/α. Many factors figure into determining β, including WB and the highly variable recombination lifetime τr. Since β
is a poorly controlled parameter with potential variations of ±50%, it is inadvisable to design circuits that depend on its exact value. Fortunately, it is usually possible to design ICs that are insensitive to β as long as β is large, say >50, thanks to matching of co-integrated devices. Figure 4.3b illustrates the well-known BJT Gummel plot, which shows the translinearity of Ic as well as the finite Ib in response to Vbe. The separation between the two curves represents β. As shown in Fig. 4.4, β represents a low frequency asymptote of h21 that exhibits
a single pole roll off toward ft at a frequency, fβ given by ft/ β. Since RFICs most often operate well above fβ, the useful measure of current gain is actually ft/f rather than β, although high DC β is still important for low noise and ease of biasing.
Traditionally, BJTs have been characterized as current-controlled devices where a forced Ib drives an Ic into an load impedance, consistent with Shockley's trans-resistor description. Now if Ib is considered a parasitic nuisance rather than a fundamental aspect, it becomes even more appropriate to view the BJT as a voltage-controlled device that behaves as a transconductor, albeit with exponential characteristics. In fact, contemporary analog IC design avoids operating the BJT as a current-controlled device due to the unpredictability of β. Instead, the designer takes advantage of device matching in an IC environment and translinearity to provide the appropriate voltage drive. This approach can be shown to be robust against device, process, temperature, and supply voltage variations. Superimposed on the basic model are parasitic ohmic resistances in series with each active terminal (Rb, Re, Rc) and parasitic capacitances associated with all pn junction depletion regions (Cjc, Cje, Cjs), including the collector-substrate junction present to some extent in all technologies. Since parasitic degrade the idealized DC and RF characteristics captured in Eqs. (4.1) and (4.5), a major effort is focused on minimizing them through aggressive scaling and process engineering. Their values and bias dependencies can be estimated from the physical device structure and layout. In particular, the base and emitter resistance, Rb and Re, soften the elegant exponential characteristics in Eq. (4.1) by essentially de-biasing the junction since
(4.8)
This effect is also illustrated in Fig. 4.3b at high values of Vbe where both curves appear to saturate. This departure from ideal translinearity can introduce unwelcome distortion into many otherwise linear ICs. Furthermore, these resistances add unwelcome noise and degeneration (voltage drops) as will be discussed later.
The idealized formulation for ft given in Eq. (4.5) also needs to be modified to account for parasitics. A more comprehensive expression for ft based on a more complex equivalent circuit results in,
(4.9)
where now ft is dependent on current through gm charging of Cje and Cjc. To achieve peak ft, high currents are required to overcome the capacitances. As the intrinsic device τf has been reduced, the parasitics have become a dominant part of the BJTs' high frequency performance requiring even higher currents to reach the lofty peak values of ft. It should also be kept in mind that ft only captures a snapshot of the device high frequency performance. In circuits, transistors are rarely current driven and short circuited at the output. The base resistance and substrate capacitance that do not appear in Eq. (4.9) can have significant impact on high frequency IC performance. While various other figures of merit such as fmax have been proposed, none can capture the complex effects of device interactions with source and load impedances in a compact form. The moral of the story is that ideal BJTs should have low inertia all around, i.e., not only high peak ft but also low parasitic capacitances and resistances, so that time constants in general can be minimized at the lowest possible currents. At the high currents required for high ft, second order phenomena known in general as high level injection begin to corrupt the DC and RF characteristics. Essentially, the electron concentration responsible for carrying the current becomes comparable to the background doping levels in the device causing deviations from the basic theory that assumes low level injection. The dominant phenomenon known as the Kirk effect or base-pushout manifests itself as a sudden widening of the base width at the expense of the collector. This translates into a departure from translinearity with dramatic drops in both β and ft. A number of other effects have been identified over the years such as Webster effect, base conductivity
modulation, and current crowding. High level injection sets a practical maximum current at which peak ft can be realized. Figure 4.5 illustrates the typical behavior of ft with Ic. To counteract high level injection, doping levels throughout the device have increased at a cost of higher depletion capacitances and lower breakdown voltages. Since modeling of these effects is very complex and not necessarily included in many models, it is dangerous to design in this regime. So far, the transistor output has been considered a perfect current source with infinite output resistance. In reality, as the output voltage swings, the base width is modulated, causing Is and thus Ic to vary for a fixed Vbe. This is exactly the effect of an output resistance and is modeled by a parameter Va, the Early voltage,
(4.10)
As illustrated in the output common-emitter characteristics, Ic vs. Vce, shown in Fig. 4.6a, Va represents the common extrapolation point where all tangents intersect the Vce axis. The effect of ro is to set the maximum small-signal unloaded voltage gain since
(4.11)
For typical values of Va = 50 V, Av = 2000 (66 dB) at room temperature. Note that this gain is independent of Ic and is quite high for a single device, representing one of the main advantages of BJTs over FETs where the maximum gain is usually limited to < 40 dB for reasonable gate lengths. In modern devices,
however, Va is not constant due to complex interactions between flowing electrons and internal electric fields. The net effect illustrated in Fig. 4.6b indicates a varying Va depending on Ic and Vce. This is often termed soft breakdown or weak avalanche in contrast to actual breakdown which will be discussed shortly. The effect of a varying Va is to introduce another form of distortion since the gain will vary according to bias point. Figure 4.7 shows a more complete model that includes the fundamental parameters as well as the parasitics and refinements considered so far. It resembles a simplified version of the popular Gummel-Poon model found in many simulators. Another form of pseudo-breakdown occurs in ultra-narrow base BJTs operating at high voltages. If the Early effect or base-width modulation is taken to an extreme, the base eventually becomes completely depleted. After this point, a further change in collector voltage directly modulates the emitter-base junction leading to an exponential increase in current flow. This phenomenon known as punchthrough fortunately has been mitigated by the fact that as base widths have narrowed, the base doping has been forced to increase so as to maintain a reasonable base resistance. Furthermore, since higher collector doping levels have been necessary to fight high level injection, true breakdown has become the voltage limiting mechanism rather than punchthrough. Just as high level injection limits the maximum operating current, junction breakdown restricts the maximum operating voltage. When the collector voltage is raised, the collector base junction is reverse biased. The resulting electric field reaches a critical point where valence electrons are literally ripped out of their energy band and promoted to the conduction band while leaving holes in the valence band. The observed effect known as avalanche breakdown is a dramatic increase in current. The breakdown of the collector-base junction in isolation, i.e., with the emitter open circuited, is termed the BVcbo where the "o" refers to the emitter open. Another limiting case of interest is when the base is open while a collectoremitter voltage is applied. In this case, an initial avalanche current acts as base current that induces more current flow, which further drives the avalanche process. The resulting positive feedback process causes the BVceo to be significantly lower than BVcbo. The relationship clearly depends on β and is empirically modeled as,
(4.12)
where n is a fit parameter. A third limit occurs when the base is AC shorted to ground via a low impedance. In this scenario, avalanche currents are shunted to ground before becoming base current and BVces ("s" means shorted) would be expected to be BVcbo+ Vbe. Therefore, BVces represents an absolute maximum value for Vce while BVceo represents a pessimistic limit since the base is rarely open. Operating in the intermediate region requires care in setting the base impedance to ground and knowing its effect on breakdown. Figure 4.8 illustrates the transition from BVceo to BVces. The base-emitter junction is also sensitive to reverse bias. In this case, the breakdown is usually related to Zener tunneling and is represented
by BVebo. Excessive excursions toward BVebo can cause injection of energetic carriers into surrounding dielectrics, leading to leakage currents, degraded reliability, and possibly device failure. Since these breakdown mechanisms in general are poorly modeled, it is recommended to operate well below BVceo and BVebo. Even when these guidelines are followed, there are still situations where peak voltages might exceed breakdown limits. For instance, modern ICs in portable products often require a disable mode in which the part consumes virtually no current so as to conserve battery life. When disabled, it is common for transistors that are normally in a safe operating condition to find themselves with reverse-biased junctions in excess of BVceo and BVebo. The resulting leakage currents can lead to expectedly high disable currents, accidental activation of certain circuit blocks, and again to potential reliability failures. A second situation is when output stages drive variable reactive loads. It is possible (and likely) that certain conditions will cause 2 to 3 times the supply voltage to appear directly across a transistor leading to certain catastrophic breakdown. As devices have been scaled down in size, isolated in dielectrics, and driven with higher current densities, self-heating has become increasingly problematic. The thermal resistance, Rth, and capacitance, Cth, model the change in junction temperature with power and the time constant of its response. The DC and AC variations in the junction temperature induce global variations in nearly all model parameters causing bias shifts, distortion, and even potentially catastrophic thermal runaway. Furthermore, local heating in one part of a circuit, say an output power stage, can start affecting neighboring areas such as bias circuits creating havoc. It is essential to selectively model thermal hotspots and ensure that they are within maximum temperature limits and that their effect on other circuit blocks is minimized by proper layout. Dynamic Range The limits on signal integrity are bounded on the low end by noise and on the high end by distortion. It is not appropriate to claim a certain dynamic range for BJTs since the circuit topology has a large impact on it. However, the fundamental noise sources and nonlinearities in BJTs can be quantified and then manipulated by circuit design. It is customary to refer the effects of noise and nonlinearity to either the input or the output of the device or circuit to allow fair comparisons and to facilitate cascaded systemlevel analyses. Here, all effects will be referred to the input, noting that the output quantity is simply scaled up by the appropriate gain. There are three fundamental noise mechanisms that are manifested in BJTs. Figure 4.9 presents a linearized small-signal model that includes the noise sources. The objective will be to refer all noise sources to equivalent voltage and current noise sources, en and in, respectively, at the input. Shot noise is associated with fluctuations in current caused by the discrete nature of electronic charge overcoming the junction potential. The presence of the forward biased base-emitter junction results in collector and base shot noise, icn, and ibn, which are given by, (4.13) where q is the electronic charge. This is a major disadvantage of BJTs with respect to FETs, which are free of shot noise due to the absence of potential barriers that determine current flow. Each physical resistance carries an associated Johnson noise represented as (4.14) where Rx is the appropriate resistance and k is Boltzmann's constant. Finally, a 1/f noise source, associated primarily with recombination at semiconductor surfaces appears at the input. The 1/f noise component decreases with increasing frequency, as expected. A corner frequency is often quoted as the point where the 1/f noise and the white thermal and shot noise cross over. It is an empirical value that varies from device to device and depends on bias conditions and source impedance. BJTs typically offer lower 1/f corner frequency than FETs since surfaces play a lesser role in BJTs. Except for broadband DCcoupled circuits and strongly nonlinear circuits such as oscillators and mixers that perform frequency conversion, 1/f noise is insignificant at high frequencies and will be ignored for simplicity. Note that treating noise in nonlinear systems is quite complex and remains an active research topic. Once the noise sources are input referred, en and in are approximately given by (4.15a) (4.15b) An arbitrarily higher Ic reduces en through the larger gm but has mixed effects on in depending on how h21(f) varies with current. An arbitrarily larger device reduces en by lowering Rb and Re but the commensurate increase in capacitance might degrade h21(f) and thus in. The moral here is that minimization of noise requires a trade-off in Ic and device size given an ft equation and parasitic scaling rules with device geometry. Distortion originates in nonlinearities within the device. For simplicity, distortion will be described in terms of a power series to derive expressions for harmonic distortion, intermodulation distortion, and compression. It is assumed that linearities up to only third order are considered, limiting the accuracy of the results as compression is approached. While this approach is valid at low frequencies, capacitive effects at higher frequencies greatly complicate nonlinear analysis and more generalized Volterra series must be invoked. However, the general idea is still valid. Note that not all systems can be mathematically modeled by power or Volterra series; for example, a hard limiting amplifier that shows sudden changes in characteristics. In BJTs, the fundamental transfer function given in Eq. (4.1) represents one of strongest nonlinearities. As shown in Fig. 4.10, by expanding Eq. (4.1) in its power series up to 3rd order, the following measures of input-referred figures of merit are derived in dBV (mV) where P1db is the 1-dB gain compression point, IIP3 is the third order intercept point, and P3OI is the third harmonic intercept point. Note that the conversion from dBV to dBm referenced to 50 Ω is + 10 dB. From the analysis, it can be inferred that P1db occurs for peak input swings of about Vt while a third order intermodulation level of 40 dBc is achieved for an input swing of only 0.0283 Vt or 0.73 mV at room temperature. These values are quite low, indicating that circuit linearization techniques must be invoked to exceed these limits. FETs on the other hand possess a more benign input nonlinearity that ranges from square law in long channel devices to nearly linear in short channels. While this is not the sole source of nonlinear behavior, FETs are expected to have superior linearity as compared to BJTs from this perspective. It is interesting to observe that the commonly used rule of thumb stating that IIP3 is approximately 10 dB higher than P1db is true in this case. As mentioned earlier, higher order terms, parasitics, and reactive effects modify the results in Eq. (4.16) but they do provide a useful order of magnitude. A common technique for extending overall dynamic range is emitter degeneration, which as illustrated in Fig. 4.11, essentially amounts to series-series feedback. The impedance in series with the emitter reduces the signal that appears directly across the emitter base leading to lower input-referred distortion. Note that the gain is proportionately reduced so that output-referred distortion is not improved to the same degree. The potentially superior distortion performance of FETs is analogous to a strongly degenerated BJT with the accompanying lower gain. Since this degenerating impedance is directly in the signal path, it also affects noise. If the impedance is a resistor, it will contribute noise as if it were an extra Re in Eq. (4.15a). If Re is not a dominant noise contributor, this approach can extend dynamic range significantly. Another option is to use a degenerating inductor, which at high frequencies provides adequate degeneration while only contributing noise associated with its finite quality factor, Q. Other feedback techniques are also possible to improve dynamic range, but care must be taken to ensure stability particularly around longer feedback loops. Additional benefits of using local feedback are desensitization of input impedance and gain to device parameters. Complementary Pnp The availability of a pnp device to complement the npn offers numerous advantages, particularly at lower supply voltages. For example, pnp active loads can provide more voltage gain at a given supply voltage; signals can be "folded" up and down to avoid hitting the rails and balanced complementary push-pull topologies can operate near rail-to-rail. In general, the p-type device is slower than the n-type device across most technologies due to the fundamentally lower hole mobility with respect to electron mobility. Furthermore, in practice, the pnp transistor is often implemented as a parasitic device, i.e., the fabrication process is optimized for the npn and the pnp shares the available layers. Figure 4.12 illustrates how two different pnp's can be constructed in an npn process (p-type substrate). The so-called substrate pnp has the substrate double as its collector and thus only appears in a grounded collector arrangement. The lateral pnp frees the collector terminal, but carries along a parasitic substrate pnp of its own that injects large currents into the substrate and degrades ft and β. In some cases, true complementary technologies are available in which both the npn's and pnp's are synthesized and optimized separately. When only lateral and substrate pnp's are available, they are usually used outside of the high-speed signal path due to their compromised RF performance. They appear prominently in bias generation and distribution as well as in low and intermediate frequency blocks. When using either pnp, care must be taken to account for current injection into the substrate, which acts locally as a collector. This current can induce noise and signal coupling as well as unintentional voltage drops along the substrate. It is customary to add substrate contacts around the pnp's to bring this current to the surface before it disperses throughout the IC. If true high-quality vertical pnp's are available that are balanced in performance with respect to the npn's, they can be used for high-frequency signal processing, enabling a number of circuit concepts commonly used at lower frequencies to be applied at RF. Topologies Several basic single-transistor and composite transistor configurations are commonly encountered in RFICs. Figure 4.13 shows the three basic single-transistor connections known as common-emitter (CE), common-base (CB), and common-collector (CC). The name refers to the fact that the common terminal is AC grounded. Their properties are well covered in numerous texts and only a brief discussion on their general properties and applications will be presented here. The CE stage is the most commonly considered configuration since it provides a fairly high input impedance, high output impedance, and both current gain, h21(f), and voltage gain, gmRL. The noise and distortion properties are the same as considered earlier for the BJT. It is commonly used in single-ended, low noise amplifiers (LNA) and power amplifiers (PA). A well-known drawback of the CE stage at high frequencies is the feedback Cjc, which degrades gain via Miller multiplication and couples input and output networks leading to detuning of matching networks and possible instability. As noted earlier, emitter degeneration can be used not only to improve dynamic range but also to help set impedance levels. It is sometimes necessary for the IC to present a standard impedance level at its input and output terminals to provide proper terminations. The use of emitter inductive degeneration has the fortuitous property of generating a synthetic resistive input impedance at high frequencies without contributing noise. As illustrated in Fig. 4.11 earlier, the transformed value is given by which now appears in series with the input terminal. The CB stage provides a well-predicted low input impedance given by 1/gm, high output impedance and voltage gain, gmRL, but has near unity current gain, α. It acts as an excellent current buffer and is often used to isolate circuit nodes. The CB appears most often in tight synergy with other transistors arranged in composite configurations. Although it lacks the capacitive feedback present in the CE that degrades gain and destabilizes operation, any series feedback at the grounded base node can lead to instability. The feedback element might be due to metallization, package parastics, or even the actual device base resistance. Extreme care must be exercised when grounding the CB stage. Another difference is that with a grounded base, the larger BVcbo sets the voltage limit. The noise and distortion properties are identical to the CE. The CC stage is often known as an emitter follower. It is predominantly used as a level shifter and as a voltage buffer to isolate stages and provide extra drive. It offers high input impedance, low output impedance, and near unity voltage gain. The impedance buffering factor is roughly h21(f) and at frequencies approaching ft, its effectiveness is diminished as h21(f) nears unity. In this case it is common to see several stages of cascaded followers to provide adequate drive and buffering. The CC stage is a very wideband stage since direct capacitive feedthrough via Cd and Cje cancels the dominant pole to first order. However, this same capacitive coupling from input to output can cause destabilization, particularly with capacitive loads. In fact, this is the basis of operation of the Colpitts oscillator. From a noise point of view, the CC simply transfers noise at its output directly back to its input and then adds on its own noise; therefore it is not used where low noise is essential. From a distortion perspective, the CC can be fairly linear as long as the impedance that it is driving is significantly higher than its own output impedance 1/gm. For minimal added shot noise and low distortion, CC stages must run at high bias currents. The strength of IC technology is the ability to use transistors at will at practically no extra cost. Figure 4.14 illustrates five very common composite transistor configurations, namely the cascode, the differential pair, the Darlington, the cross-coupled pair, and the current mirror. These ubiquitous forms are common enough to be considered in more detail. Discussion of the current mirror appears later. The cascode topology is a CE-CB connection. The CB provides a low impedance to the output of the CE stage, eliminating Miller multiplication of its Cjc and increasing the overall bandwidth. It also raises the output impedance of the single transistor by a factor of approximately β, which is useful in current sources. More importantly at RF, it improves input-output isolation, minimizing interactions that reduce the gain. The cascode configuration is common in LNAs since higher tuned power gain is achievable with minimal degradation in noise. Note that the CB transistor can be significantly smaller than the CE transistor, minimizing the parasitic capacitance at its output. The cascode requires a higher supply voltage than a stand-alone CE stage by at least a Vce(sat) to keep the lower BJT in its active region. The differential pair (also known as a long-tailed pair) can be thought of as a CC-CB connection when driven in a single-ended fashion or as parallel CE stages when driven differentially. A tail current source or a current setting resistance is required to establish the operating point. This ubiquitous, canonical form has a long, distinguished history in operational amplifiers, mixers, IF/RF amplifiers, digital ECL/CML gates, and even oscillators and latches when cross-coupled. The basic operation relies on the controlled steering of current from one branch to the other. Notice that the dynamic range is modified by the fact that noise sources from two transistors contribute to the total noise while the signal is divided across two junctions. The noise associated with the tail current source appears as common mode noise and does not affect the input noise if differential signaling is used. The structure can be enhanced with the addition of emitter degeneration, cascoding CB stages, and buffering CC stages. The Darlington connection is a CE stage buffered at the input by CC stage. This configuration behaves essentially like a super-transistor with greater impedance buffering capability and higher h21(f). It typically appears at input and output interfaces where drive and buffering requirements are most severe. The Darlington and the differential pair are sometimes called ft multipliers since the input signal appears across two transistor junctions in series while the output signal is a parallel combination of currents. For a fixed input bias current per device, the effective input capacitance is Cd /2 while the effective transconductance is still gm, giving from Eq. (4.5) an ft eff = 2ftBJT. This of course ignores additional higher order poles and requires twice the current of a single BJT. In analogy to the differential pair, noise and distortion occur across two junctions in series. The cross-coupled connection is derived from the differential pair. Following the signals around the loops leads to a positive feedback condition that can be used to induce regeneration for Schmidt triggers, multivibrators, and latches or negative resistance for tuned VCOs and gain peaking. It has also been used to synthesize voltage-to-current converters, bias cells, multipliers, and other functions. Since positive feedback is inevitably invoked in cross-coupled devices, care must be taken to avoid instability when it is undesired. Note that npn-pnp composite structures are also possible creating many permutations that might offer certain advantages. These are illustrated in Fig. 4.15 in the form of the double up-down emitter-follower, the folded cascode, the composite pnp, and complementary mirror. The first two examples reduce the supply voltage requirements over their npn-only embodiment, the third transforms a poor quality pnp into a nearly ideal device, and the fourth provides a voltage controlled mirror ratio. Translinear Circuits The concept of translinearity was observed in deriving the basic properties of BJTs and its usefulness was alluded to in general terms. In particular, if the signals of interest are conveyed as currents rather than voltages, a large class of linear and nonlinear functions can be synthesized. When current-mode signals are used, extremely large dynamic ranges are possible since the junction essentially compresses the current signal logarithmically to a voltage; i.e., a 60 dB (1000x) signal current range corresponds to 180 mV of voltage swing at room temperature. The relatively small voltage swings represent low impedance through which capacitances charge and discharge and thus the bandwidth of these circuits achieves broadband operation out to near the device limits represented by ft. Furthermore, reduced internal voltage swings are consistent with lower supply voltages. The simplest example of a translinear circuit is the well-known current mirror shown in Fig. 4.14. The input current, Iin, is mirrored to the output, Iout according to a scaling factor associated with the ratio of device sizes. Inherent in this process is a nonlinear conversion from Iin to the common Vbe and then a second related nonlinear conversion from Vbe to Iout. The impedance at the common base node is nominally a parallel combination of 1/gm and (1 + A)Cd, which results in a low time constant on the order of τf . A large family of translinear circuits has been synthesized by applying the translinear principle stated as: In a closed loop containing only junctions, the product of current densities flowing in the clockwise direction is equal to the product of current densities flowing in the counterclockwise direction. The principle has a corollary when voltage sources are inserted into the loop, namely that the products are equal to within a factor exp(Va/Vt), where Va is the applied voltage. It is merely a restatement that logarithmic multiplication and division, i.e., addition and subtraction of Vbe's, is tantamount to products and quotients of currents. In this sense, the BJT can be thought of as the mathematical transistor. Note that since the signals are in current form, the distortion is not caused by the exponential characteristics but is actually due to departure from it, i.e., series resistances, high level injection, and early voltage effects conspire to distort the signals. Fig. 4.16 illustrates three examples of translinear IC design. The first example is an analog squarer/ divider with input signals Ix, Iy and output, Io. By following the translinear principle, it can be shown that the mathematical operation (4.18a) is performed. The second example is the well-known Gilbert-cell multiplier/gain cell with predistortion. Again, by following the rules, the differential output currents have the same form as the two inputs. The third example is a linear in dB variable gain amplifier. In this case a voltage Vg = RgIg is inserted into the loop and Eq. (4.18a) is modified so that (4.18b) Note that if Vg and Ix are engineered to be proportional to temperature, then the gain control becomes stable with temperature. In all cases, the operating frequency of these circuits approaches the technology ft. Biasing Techniques Microwave IC designers have historically focused on the signal path with biasing treated as an afterthought. Analog IC designers, on the other hand, have placed a strong emphasis on biasing since it usually determines the sensitivity and robustness of a circuit. In particular, as was already seen in the variable gain amplifier, it is often necessary to generate a current that is proportional to absolute temperature, PTAT. Other times it is necessary to generate a current that is complementary to absolute temperature, CTAT. Finally sometimes a zero temperature coefficient current, ZTAT, is desired. The choice on tem- perature shaping depends on what is needed. In differential amplifiers where the gain is given by gmRL = IoRL/2Vt, it is appropriate to choose a PTAT bias current for a stable gain; however, if the amplifier is actually a limiter, then a stable limited voltage swing requires a ZTAT shaping. By far the most common and fundamental bias current shape for BJTs turns out to be PTAT. From the PTAT form, other shapes can be derived. The fundamental way to synthesize a bias sub-circuit is to start with a ΔVbe cell that generates a PTAT current. This cell, illustrated in Fig. 4.17, is a modified translinear loop. Two area ratioed BJTs each forced to carry the same current generate a difference in Vbe given by (4.19) where A is the area ratio. This voltage develops a current in R that is PTAT and can now be mirrored throughout the IC by adding a driver that buffers the ΔVbe cell. In some cases, a stable voltage reference is desired for scaling and it is beneficial to derive the various currents from this reference. To achieve a stable reference, the bandgap principle is invoked. As illustrated in Fig. 4.18, the idea is to add a CTAT voltage to a PTAT voltage so that the sum is a constant with temperature. It can be shown that the desired reference voltage Vg nearly corresponds to the bandgap energy, Eg of silicon, a very fundamental property. Intuitively, this is expected since at the extreme temperature of 0 K, it takes an energy equivalent to Eg to promote an electron into conduction. It so happens that a transistor Vbe at a fixed Ic can be shown to be CTAT while a PTAT voltage can be generated from the ΔVbe cell. With this in mind, the PTAT component should be scaled such that it adds to the CTAT component to synthesize Vg. A physical realization of this principle known as a bandgap reference is illustrated in its simplest form in Fig. 4.19. It consists of a ΔVbe cell to generate a PTAT current and a resistor that converts it to the required PTAT voltage. Transistor Q1 plays a double role as part of the ΔVbe cell and as the Vbe responsible for the CTAT voltage. The current mirror above ensures that both currents are the same and the buffer provides drive to the reference output. This output can be used to generate PTAT currents elsewhere in the circuit as shown in Fig. 4.19. The target transistor and resistor scaling are necessary to preserve the PTAT shape. This topology can be made insensitive to supply voltage, temperature, and process variations by the use of more sophisticated cells and by the prudent choice of component sizes and layout. Fabrication Technology The technology for fabricating BJTs has been performance and cost driven toward smaller transistor geometries, lower device and interconnect parasitics, higher yield/integration, and greater functionality. Silicon-based BJT technology has benefited greatly from the synergy with CMOS processes targeting VLSI/ULSI digital applications. Several variants of the simple npn process have evolved over the years that feature better npn's and/or addition of other transistor types. Examples include BiCMOS, which integrates BJTs with CMOS; fully complementary bipolar with true vertical npn's and pnp's; SiGe/Si HBT, which offers higher ft and lower Rb than traditional BJTs; and silicon-on-insulator (SOI) processes that rely on an insulating substrate to isolate devices and reduce substrate parasitics. III-V based HBTs have developed in a different direction since raw device speed has been more than adequate, but integration levels and process complexity have limited their availability. Process features can be grouped into two general categories: the active device, which determines the transistor performance, and the back-end process, which defines the interconnect metallization, dielectric isolation, passive components, and through-vias. The back-end process is particularly critical in RFICs since they set limits to IC parasitic and are responsible for the quality of resistors, capacitors, and inductors. The silicon BJT process has evolved from the junction isolated buried collector process shown in Fig. 4.12 to the oxide trench isolated double-poly (emitter and base) process diagrammed in Fig. 4.20. The double poly structure with self-aligned spacers allows ultra-small emitter-base structures to be defined while simultaneously providing low extrinsic base resistance and low emitter charge storage. A selective collector implant under the active emitter helps delay the Kirk effect without significantly increasing the depletion capacitance. In general, the devices are defined by diffusions into the substrate with interconnects and passives constructed over dielectrics above the substrate. Standard aluminum metals have been silicided for improved reliability. Overall, this has led to significantly reduced device footprints and feature sizes with emitter geometries down to < 0.35 μm and ft ranging from 30 GHz for standard BJTs to > 100 GHz for SiGe HBTs. Refinements such as silicided base handles and optimized epitaxially deposited bases promise even further improvements in device performance. On the back-end side, thin-film resistors and metal-metal capacitors are replacing their polysilicon and diffused versions bringing lower temperature coefficients, reduced parasitics and coupling to the substrate, trimming capability, and bias insensitivity. Furthermore, advanced multiple level interconnect modules and planarization techniques have been adopted from CMOS processes in the form of copper metalization, chemical-mechanical polishing, tungsten plugs, and low dielectric insulators. For RFICs, advanced interconnects are desirable not for high packing density, but for defining high quality passives away from the lossy substrate, particularly inductors, which are essential in certain applications. The fabrication technology for the III-V HBTs is significantly different from that of silicon BJTs. The main difference stems from the fact that the starting material must be grown by advanced epitaxial techniques such as molecular beam epitaxy (MBE) or metallo-organic chemical vapor deposition (MOCVD). Each layer in the stack is individually optimized as needed. As a result of the predefined layers as well as thermal limits that disallow high temperature diffusion, the device is literally carved into the substrate leading to the wedding-cake triple mesa structure depicted in Fig. 4.21. The nature of the process limits minimum emitter geometries to about 1 μm, although self-aligned structures are used to minimize extrinsic areas. Values of ft range from 30 GHz for power devices to 200 GHz for the highest speed structures. Interestingly, the improvements being made to silicon BJTs such as epitaxial bases, polysilicon emitters, and silicided bases, make use of deposited active layers, which is reminiscent of III-V technologies based on epitaxy. The back-end process inevitably consists of thin film resistors and metalmetal capacitors. Since the substrate is semi-insulating by definition, high-Q monolithic inductors are already available. Some processes offer backside vias that literally provide a direct connection from the front-side to the back-side of the wafer enabling easy and effective grounding at any point on the circuit. 5. Heterostructure Bipolar Transistors (HBTs). Basic Device Principle Heterojunction bipolar transistors (HBTs) differ from conventional bipolar junction transistors (BJTs) in their use of hetero-structures, particularly in the base-emitter junction. In a uniform material, an electric field exerts the same amount of force on an electron and a hole, producing movements in opposite directions as shown in Fig. 5.1a. With appropriate modifications in the semiconductor energy gap, the forces on an electron and a hole may differ, and at an extreme, drive the carriers along the same direction as shown in Fig. 5.1b. The ability to modify the material composition to independently control the movement of carriers is the key advantage of adopting hetero-structures for transistor design. Figure Fig. 5.2 illustrates the band diagram of a npn sound three-terminal device. As the input and output ports are decoupled from one another, complicated circuits based on the transistors can be easily designed. The second current component is composed of holes that are back-injected from the base to the emitter. This current does not get collected at the collector terminal and does not contribute to the desired output signal. However, the moment a VBE is applied so that the desired electrons are emitted from the emitter to the base, these holes are back-injected from the base to the emitter. The bipolar transistor is so named to emphasize that both electron and hole play significant roles in the device operation. A good design of a bipolar transistor maximizes the electron current transfer while minimizing the hole current. As indicated on Fig. 5.2, we refer the hole current as IB, back-inject. It is a base current because the holes come from the base layer where they are the majority carriers. We mentioned that IC is limited by the diffusion process in the base, wherein the electrons are minority carriers. Likewise, IB ,back-inject is limited by the diffusion in the emitter, wherein the holes are minority carriers. Fisk's law states that a diffusion current density across a layer is equal to the diffusion coefficient times the carrier concentration gradient. (From the Einstein relationship, the diffusion coefficient can be taken to be kT/q times the carrier mobility.) The carrier concentrations at one end of the base layer (for the calculation of IC) and the emitter layer (for the calculation of IB, back-inject) are both proportionalto exp(qVBE/kT), and are 0 at the other end. An application of Fisk's Law leads to: where, for example, A emitis the emitter area; Dn, base is the electron diffusion coefficient in the base layer; N base is the base doping; X base is the base thickness; and ni, base is the intrinsic carrier concentration in the base layer. IC is proportional to the emitter area rather than the collector area because IC is composed of the electrons injected from the emitter. For homojunction BJTs, ni, base is identical to ni, emit. The ratio of the desired IC to the undesired IB, back-inject is, Because the diffusion coefficients and layer thicknesses are roughly equal on the first order, Eq. (5.3) demonstrates that the emitter doping of a BJT must exceed the base doping in order for IC to exceed IB, back-inject. For most applications, we would actually prefer the base doping be high and the emitter doping, low. A high base doping results in a small base resistance and a low emitter doping reduces the baseemitter junction capacitance, both factors leading to improved high frequency performance. Unfortunately, these advantages must be compromised in the interest of minimizing IB, back-inject in homojunction transistors. A heterojunction bipolar transistor (HBT), formed by a replacement of the homojunction emitter by a larger energy gap material, enables the design freedom of independently optimizing the IC/IB, back-inject ratio and the doping levels. Figure 5.3 illustrates the band diagrams of Npn HBTs. The capital N in "Npn" rather than a small letter n emphasizes that the emitter is made of a larger energy gap material than the rest. It is implicit that the base-collector junction of an HBT is a homojunction. An HBT whose basecollector junction is also a heterojunction is called a double heterojunction bipolar transistor (DHBT), typically found in the InP/InGaAs material system. The energy gap difference in the base-emitter heterojunction of an HBT burdens the holes from the base to experience a much larger energy barrier than the electrons from the emitter. With the same application of VBE, the forces acting on the electrons and holes differ, favoring the electron injection from the emitter into the base to the hole back-injection from the base into the emitter. Figure 5.3 shows that the difference in the electron and hole barriers is Δ Ev, the valence band discontinuity. The IC/IB, back-inject ratio of Eq. (5.3) can be extended to the HBT as: The exponential factor is the key to the fact that base doping can be made larger than the emitter doping without adversely affecting the HBT performance. We qualify the expression in Eq. (5.4): that is for an abrupt HBT. This means that an abrupt change of material composition exists between the emitter and the base. An example is an InP/In0.53Ga0.47As HBT. The indium and gallium compositions form a fixed ratio so that the resulting In0.53Ga0.47As layer has the same lattice constant as InP, the starting substrate material. Otherwise, the dislocations due to lattice mismatch prevent the device from being functional. In fact, although the idea of HBT is as old as the homojunction transistor itself, HBTs have emerged as practical transistors only after molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) were developed to grow highquality epitaxial layers in the 1980s. Another example of an abrupt HBT is the Al0.3Ga0.7As/GaAs HBT, in which the entire emitter layer consists of Al0.3Ga0.7As, while the base and collector are GaAs. When the AlGaAs/GaAs material system is used, we can take advantage of the material property that AlAs and GaAs have nearly the same lattice constants. It is therefore possible to grow an AlxGa1-x As layer with any composition x and still be lattice-matched to GaAs. When the aluminum composition of an intermediate AlGaAs layer is graded from 0 at the GaAs base to 30% at the Al0.3Ga0.7As emitter, then the resulting structure is called a graded HBT. The band diagram of a graded HBT is shown in Fig. 5.4. A graded HBT has the advantage that the hole barrier is larger than the electron barrier by ΔEg, the energy-gap discontinuity between the emitter and the base materials. Previously, in an abrupt HBT, the difference in the hole and electron barriers was only ΔEv. The additional barrier brings forth an even larger IC /IB,back-inject ratio for the graded HBT: Equation (5.5) is obtained from the inspection of the band diagram. It is also derivable from Eqs. (5.1) and (5.2) by noting that ni,base 2 = ni,emit 2 × exp(ΔEg/kT). The amount of improvement from a homojunction to a heterojunction depends on the band alignment properties of the two hetero-materials. Table 5.1 lists the conduction band discontinuity (ΔEc), valence band discontinuity (ΔEv), and their sum which is the energy-gap discontinuity (ΔEg), for several material systems used for HBTs. The energy gap of a semiconductor in the system is also given for convenience. The values shown in Table 5.1 are room temperature values. The most popular III-V material system is AlxGa1-xAs/GaAs. The table lists its band alignment parameters for x ≤ 0.45. At these aluminum mole fractions, the AlGaAs layer is a direct energy-gap material, in which the electron wave function's wave vectors k at both the conduction band minimum and the valence band maximum are along the same crystal direction.2 Since nearly all semiconductor valence band maximums take place when k is [000], the conduction band minimum in a direct energy-gap material is also at k = [000]. The conduction band structure surrounding this k direction is called the Γ valley. There are two other k directions of interest because the energy band structures in such directions can have either the minimum or a local minimum in the conduction band. When k is in the [100] direction, the band structure surrounding it is called the X valley, and when k is in the [111] direction, the L valley. As the aluminum mole fraction of AlxGa1-xAs exceeds 0.45, it becomes an indirect energygap material, with its conduction band minimum residing in the X valley. The band alignment parameters at x > 0.45 are found elsewhere.3 SiGe is an indirect energy-gap material; its conduction band minimum is also located in the X valley. Electron-hole generation or recombination in indirect energy-gap materials requires a change of momentum (p = hk), a condition that generally precludes them from being useful for laser or light-emitting applications. Particularly due to the perceived advantage in improved reliability, HBTs made with the GaInP/GaAs system have gained considerable interest.7 The band alignment of GaInP/GaAs depends on whether the grown GaInP layer is ordered or disordered, as noted in Table 5.1. The crystalline structure in an ordered GaInP layer is such that sheets of pure Ga, P, In, and P atoms alternate on the (001) planes of the basic unit cell, without the intermixing of the Ga and In atoms on the same lattice plane.8 When the Ga, In and P atoms randomly distribute themselves on a plane, the GaInP layer is termed disordered. The processing of AlGaAs/GaAs and GaInP/GaAs HBTs is fairly simple. Both wet and dry etching are used in production environments, and ion implantation is an effective technique to isolate the active devices from the rest. The processing of InP/InGaAs and InAlAs/InGaAs materials, in contrast, is not straightforward. Because of the narrow energy-gap of the InGaAs layer, achieving an effective device isolation often requires a complete removal of the inactive area surrounding the device, literally digging out trenches to form islands of devices. Further, the dry-etching, and its associated advantages such as directionality of etching, is not readily/easily available for InGaAs.9 However, the material advantages intrinsic to InP/InGaAs and InAlAs/InGaAs make them the choice for applications above 40 GHz. In addition, the turn-on voltage, the applied VBE giving rise to a certain collector current, is smaller for HBTs formed with InGaAs base compared to GaAs base (due to the energy-gap difference). The turnon characteristics of various HBTs are shown in Fig. 5.5. A calculation illustrates the advantage of an HBT. Consider an AlGaAs/GaAs HBT structure designed for power amplifier applications, as shown in Fig. 5.6.10 The emitter and the base layers of the transistor are: Nemit = 5 × 1017 cm–3; Nbase = 4 × 1019 cm–3; Xemit ≈ 1300 Å; and Xbase = 1000 Å. We shall use the following diffusion coefficients for the calculation: Dn,base = 20 and Dp,emit = 2.0 cm2/V-s. For a graded Al0.3Ga0.7As/GaAs heterojunction, ΔEg is calculated from Table 5.1 to be 0.3 × 1.247= 0.374 eV. The ratio for the graded HBT, according to Eq. (5.5), is, For an abrupt Al0.3Ga0.7As/GaAs HBT, ΔEv is the parameter of interest. According to the table, ΔEv at x = 0.3 is 0.55 × 0.3 = 0.165 eV. Therefore, Eq. (5.4) leads to: Consider a Si BJT with identical doping levels, layer thicknesses, and diffusion coefficients, except that it is a homojunction transistor so that ΔEg = 0. Using Eq. (5.3), we find the IC /IB,back-inject ratio to be: The useful collector current in the homojunction transistor is only 1/6 of the undesirable back-injection current. This means the device is useless. In contrast, both the graded and the abrupt HBTs remain functional, despite the higher base doping in comparison to the emitter. Base Current Components IB, back-inject is only one of the five dominant base current components in a bipolar transistor. We have thus far considered only IB,back-inject because it is the distinguishing component between a HBT and a BJT. Once IB,back-inject is made small in a HBT through the use of a heterojunction, the remaining four components become noteworthy. All of these components are recombination currents; they differ only in the locations where the recombinations take place, as shown in Fig. 5.7. They are: (1) extrinsic base surface recombination current, IB,surf ; (2) base contact surface recombination current, IB,cont; (3) bulk recombination current in the base layer, IB,bulk; and (4) space-charge recombination current in the base-emitter junction depletion region, IB,scr . In the discussion of bipolar transistors, an easily measurable quantity of prime importance is the current gain (β), defined as the ratio of IC to the total base current IB: (5.6) Depending on the transistor geometrical layout, epitaxial layer design, and the processing details that shape each of the five base current components, the current gain can have various bias and temperature dependencies. In the following, the characteristics of each of the five base components are described, so that we can better interpret the current gain from measurement and establish some insight about the measured device. Figure 5.8a illustrates a schematic cross-section of an HBT. Without special consideration, a conventional fabrication process results in an exposed base surface at the extrinsic base regions. (Intrinsic region is that underneath the emitter, and extrinsic region is outside the emitter mesa, as shown in Fig. 5.7.) Because the exposed surface is near the emitter mesa where the minority carrier concentration is large, and because the surface recombination velocity in GaAs is high (on the order of 106 cm/s), IB,surf is significant in these unpassivated devices. Various surface passivation techniques have been tested. The most effective method is ledge passivation,11,12 formed with, for example, an AlGaAs layer on top of the GaAs base. The AlGaAs ledge must be thin enough so that it is fully depleted by a combination of the free surface Fermi level pinning above and the base-emitter junction below. If the passivation ledge is not fully depleted, the active device area would be much larger than the designed emitter. The requirement for the AlGaAs layer to be fully depleted limits the AlGaAs thickness to the order of 1000 Å, and emitter doping to low to mid 1017 cm–3. Although the ledge passivation was originally designed to minimize IB,surf, it is also crucial to long-term reliability.3,7 Unlike IC, IB,surf is proportional to the emitter periphery rather than the emitter area. For high frequency devices whose emitter is in a strip form (thus the perimeter-to-area ratio is large), IB,surf is a major component to the overall base current. The current gain is substantially reduced from that of a large squarish device whose perimeter-to-area ratio is small. The discrepancy in β due to emitter geometry is termed the emitter-size effect. Figure 5.9 displays β vs. IC for both passivated and unpassivated devices with Aemit = 4 × 10 μm2. The emitter area is small enough to demonstrate the benefit of the surface passivation. A large device has negligible surface recombination current and the current gain does not depend on whether the surface is passivated or not. Because the two devices are fabricated simultaneously and physically adjacent to each other, the difference between the measured βs is attributed to the additional IB,surf of the unpassivated device. The second base recombination current, IB,cont, is in principle the same as IB,surf. Both are surface recombination currents, except IB,cont takes place on the base contacts whereas IB,surf, on the extrinsic base surfaces. Because the contacts are located further away from the intrinsic emitter than the extrinsic base surface, IB,cont is generally smaller than IB,surf when the surface is unpassivated. However, it may replace IB,surf in significance in passivated devices (or in Si BJTs whose silicon dioxide is famous in passivating silicon). There is a characteristic distance for the minority carrier concentration to decrease exponentially from the emitter edge toward the extrinsic base region.3 As long as the base contact is placed at roughly 3 times this characteristic length away from the intrinsic emitter, IB,cont can be made small. The base contact cannot be placed too far from the emitter, however. An excessively wide separation increases the resistance in the extrinsic base region and degrades the transistor's high frequency performance. The above two recombination currents occur in the extrinsic base region. Developing analytical expressions for them requires a solution of the two-dimensional carrier profile. Although this is possible without a full-blown numerical analysis,3 the resulting analytical equations are quite complicated. The base bulk recombination current, in contrast, can be accurately determined from a one-dimensional analysis since most of the base minority carriers reside in the intrinsic region. It is convenient to express IB, bulk through its ratio with IC: (5.7) where τn is the minority carrier lifetime in the base, and τb, the minority carrier transit time across the base. In a typical Si BJT design, an electron spends about 10 ns diffusing through the base layer while in every 1 μs an electron is lost through recombination. The transistor then has a current gain of 1 μs/10 ns = 100. The recombination lifetime in the GaAs base material is significantly shorter than in Si, at about 1 ns. However, the transit time through the GaAs is also much shorter than in Si due to the higher carrier mobility in GaAs. A well-designed HBT has a τb of 0.01 ns; therefore, a β = 100 is also routinely obtainable in III-V HBTs. Equation (5.7) indicates that IB,bulk is large if τn is small. The recombination lifetime of a semiconductor, a material property, is found to be inversely proportional to the doping level. When the base doping in an AlGaAs/GaAs (or GaInP/GaAs) HBT is 5 × 1018 cm–3, the current gain easily exceeds 1000 when proper device passivation is made and the base contacts are placed far from the emitter. As the base doping increases to 1020 cm–3, IB,bulk dominates all other base current components, and the current gain decreases to only about 10, independent of whether the extrinsic surface is passivated or not. The base doping in III-V HBTs for power applications, as shown in Fig. 5.6, is around 3 – 5 × 1019 cm–3. It is a compromise between achieving a reasonable current gain (between 40 and 200) and minimizing the intrinsic base resistance to boost the high frequency performance. Equation (5.7) also reveals that IB,bulk is large when the base transit time is long. This is the time that a base minority carrier injected from the emitter takes to diffuse through the base. Unlike the carrier lifetime, which is mostly a material constant, the base transit time is a strong function of the base layer design: (5.8) Because τb is proportional to the square of Xbase, the base thickness is designed to be thin. Making the base too thin, however, degrades high frequency performance due to increased base resistance. A compromise between these two considerations results in a Xbase at around 800 – 1000 Å, as shown in Fig. 5.6. The derivation of Eq. (5.8) assumes that the minority carriers traverse through the base purely by diffusion. This is certainly the scenario in a bipolar transistor whose base layer is uniformly doped and of the same material composition. With energy-gap engineering, however, it is possible to shorten the base transit time (often by a factor of 3) by providing a drift field. In a Si/SiGe HBT for example, the Ge content can be linearly graded from 0 to 8% across a 300 Å base to result a quasi-electric field on the order of 30 to 50 kV/cm.13 We used the term quasi-electric field to describe the electric field generated by grading the energy gap, or more specifically, the gradient of the electron affinity (χe). In a conventional bipolar transistor, an electric field can be established only in the presence of space charges (such as the depletion region in a p-n junction). In an HBT with a graded base, the overall electric field in the base layer is nonzero even though the entire base region remains charge neutral. A SiGe HBT band diagram, shown in Fig. 5.10, illustrates how a minority carrier can speed up in the presence of the band grading. The figure shows that the energy gap becomes narrower as the Ge content increases. Because the base layer is heavily doped, the quasi-Fermi level in the base is pinned to be relatively flat with respect to position. The entire energy gap difference appears in the conduction band. The base quasi-electric field, being proportional to the slope of the band bending, propels the electrons to drift from the emitter toward the collector. As the carrier movement is enhanced by the drift motion, in addition to the diffusion, the base transit time decreases. Figure 5.10 is characteristic of the SiGe HBT pioneered by a U.S. company,14 in which the Ge content is placed nearly entirely in the base and graded in a way to create a base quasi-electric field. The baseemitter junction is practically a homojunction; therefore, it perhaps does not strictly fit the definition of being a heterojunction bipolar transistor and the base must be doped somewhat lighter than the emitter. This type of transistor resembles a drift homojunction transistor,15 in which a base electric field is established by grading the base doping level. A drift transistor made with dopant grading suffers from the fact that part of the base must be lightly doped (at the collector side), thus bearing a large base resistance. An alternative school of SiGe HBT places a fixed Ge content in the base, mostly promoted by European companies.16 Transistors fabricated with the latter approach do not have a base quasi-electric field. However, the existence of the base-emitter heterojunction allows the emitter to be more lightly doped than the base, just as in III-V HBTs. In either type of SiGe HBTs, there can be a conduction band discontinuity between the base and collector layers. This base-collector junction spike (Fig. 5.10), also notable in InP-based DHBT, has been known to cause current gain fall off.3 The spike can be eliminated by grading the Ge content from the base to inside the collector layer. Likely due to reliability concerns or for purely historical reasons, most commercial III-V HBTs have a uniformly doped base without a base quasi-electric field. If a base electric field is desired, in AlGaAs/"GaAs" HBTs in particular, the field can be established by grading of the aluminum concentration in the AlGaAs base layer. The fourth recombination current is the space-charge recombination current in the base-emitter depletion region. IB,scr differs from the other base current components in its bias dependency Equations (5.1) and (5.2) show that IC and IB,back-inject are proportional to exp(qVBE /nkT) with n, the ideality factor, being equal to 1. Equation (5.7) also shows that IB,bulk is directly proportional to IC. Hence, IB,bulk has a unity ideality factor as well. Extensive measurement experiments and theoretical calculations indicate that IB,surf and hence, IB,cont, have an ideality factor closer to 1 than 2.3,17 The ideality factor of IB,scr, in contrast, is nearly 2 because the electron and hole concentrations in the forward-biased baseemitter junction are both proportional to exp(qVBE /2kT).2 This means IB,scr is most significant when VBE is small, at which operating region IC is also small. A Gummel plot, IB and IC as a function of VBE taken at VBC = 0, illustrates dominance of IB,scr in low-current regions, as shown in Fig. 5.11. There are times when IB,scr dominates other base current components even at high IC levels, particularly in graded HBTs. The previous four base current components are all recombination current. The fifth component is the back-injection current, IB,back-inject. This component is made small in a heterojunction transistor, at least at room temperature. However, as temperature increases, the extra energy barrier provided to the hole carriers becomes less effective in impeding the back injection. When the HBT is biased with a high IC and a certain amount of VBC, the power dissipated in the device can heat up the device itself (called selfheating). As the HBTs junction temperature rises, IB,back-inject increases and the current gain decreases. This β's temperature dependency is to be contrasted with silicon BJTs current gain, which increases with temperature. Kirk Effects Understanding the properties of the various base current components facilitates the description of the measured device characteristics, such as the β vs. IC curve of Fig. 5.9. The previous analysis of the transistor currents implicitly assumes that the transistor operates in the normal bias condition, under which the transistor gain is seen to increase steadily with the collector current. However, IC cannot increase indefinitely without adverse effects. Figure 5.9 reveals that, after a certain critical IC is reached while VBC is kept constant, the current gain plummets, rendering the device useless. For high-power applications, such as a power amplifier for wireless communications, HBTs are biased at a large current (with a current density on the order of 104 A/cm2), not only because the output power is directly proportional to IC, but also because the high frequency performance is superior at large IC (but before the current gain falls). Therefore, it is imperative to understand the factor setting the maximum IC level, below which the current gain is maintained at some finite values. The Poisson equation relates charges to the spatial variations of the electric field (ε).2 It is a fundamental equation, applicable to any region at any time in a semiconductor: (5.9) ∈s is the dielectric constant of the semiconductor; Nd and Na are the donor and acceptor doping levels, respectively; and n and p are the mobile electron and hole carrier concentrations, respectively. We apply this equation to the base-collector junction of HBTs, which is typically a homojunction. Since the base doping greatly exceeds the collector doping, most of the depletion region of the base-collector junction is at the collector side. In the depleted collector region where it is doped n-type, Nd in Eq. (5.9) is the collector doping level, Ncoll, and Na is 0. The collector current flowing through the junction consists of electrons. If the field inside the depletion region was small, then these electrons would move at a speed equal to the product of the mobility and the electric field: μn ·ε. It is a fundamental semiconductor property that, once the electric field exceeds a certain critical value (εcrit ~ 103 V/cm for GaAs), the carrier travels at a constant velocity called the saturation velocity (vsat). Because the electric field inside most of the depletion region exceeds 104 V/cm, practically all of these electrons travel at a constant speed of vsat . The electron carrier concentration inside the collector can be related to the collector current density (JC; equal to IC /Aemit) as: (5.10) Lastly, because there is no hole current, p in Eq. (5.9) is zero. Equation (5.9), when applied to the base-collector junction of a HBT, is simplified to: (5.11) When JC is small, the slope of the electric field is completely determined by the collector doping, Ncoll. Because the doping is constant with position, solving Eq. (5.11) at negligible JC gives rise to a field profile that varies linearly with position, as shown in Fig. 5.12a. As the current density increases, the mobile electron concentration constituting the current partially cancels the positive donor charge concentration Ncoll. As the net charge concentration decreases, the slope of the field decreases, as shown in Fig. 5.12b. While the current density increases, the base-collector bias VBC remains unchanged. Therefore, the enclosed area of the electric field profile, which is basically the junction voltage, is the same before and after the current increase. The simultaneous requirements of having a decreasing field slope and a constant enclosed area imply that the depletion region extends toward the subcollector layer and the maximum electric field decreases. The depletion thickness continues to increase until the collector is fully depleted, as shown in Fig. 5.12c. The depletion thickness does not extend beyond the collector layer because the subcollector is a heavily doped layer. Afterwards, further increase of current results in a quadrangle field profile, as shown in Fig. 5.12d, replacing the previous triangular profile. As the current density increases to a level such that JC = qNcoll ·vsat, the term inside the parentheses of Eq. (5.11) becomes zero. A field gradient of zero means that the field profile stays constant with the position inside the junction (slope =0). This situation, depicted in Fig. 5.12e, marks the beginning the field reversal. When JC increases further such that JC > qNcoll ·vsat , the mobile electrons brought about by the collector current more than compensates the fixed charges inside the collector. The net charge concentration for the first time becomes negative and the electric field takes on a negative slope (Fig. 5.12f), with a smaller magnitude at the base side of the junction than at the subcollector side. As the trend progresses, the magnitude of the field base-collector junction eventually diminishes to zero (Fig. 5.12g). When there is no more field to block the holes from "spilling" into the collector, the base pushout is said to occur and the current gain falls. The device characteristics as a result of the base pushout are referred to as Kirk effects.19 The above description suggests that the threshold current due to Kirk effects increases if the collector doping increases. However, in many applications where the collector doping may not be increased arbitrarily (so the operating voltage is greater than a certain value), Kirk effects then become an important mechanism affecting the current gain falloff in HBTs. For an HBT with a collector doping of 3 × 1016 cm–3 (Fig. 5.6), the threshold current density is roughly JC = qNcoll ·vsat = 3.9 × 104 A/cm2 (vsat is ~ 8 × 106 cm/s). Clearly, the value of such threshold current density depends on the magnitude of the saturation velocity. Since the saturation velocity decreases with the ambient temperature, the threshold density due to Kirk effects is lower at higher temperatures. Kirk effects confine the operating collector current to some values. Similarly, the collector-to-emitter bias (VCE) has its limit, set by two physical phenomena. The first one, well analyzed in elementary device physics, is the avalanche breakdown in the base-collector junction. The base-collector junction is a reverse-biased junction with a finite electric field. The mobile electrons comprised of JC, while moving through the junction, quickly accelerate and pick up energy from the field. When VCE is small, the magnitude of the field is not too large. The energy the carriers acquired is small and is quickly dissipated in the lattice as the carriers impact upon the lattice atoms. The distance within which a carrier travels between successive impacts with the lattice atoms is called a mean free path. As VCE increases such that the electric field approaches 105 – 106 V/cm, the energy gained by a carrier within one mean free path can exceed the energy gap of the collector material. As the highly energetic carrier impacts the lattice atoms, the atoms are ionized. The act of a carrier impacting the lattice and thereby creating electronhole pairs is called impact ionization. One single impact ionization creates an electron-hole pair, which leads to further impact ionization as the recently generated carriers also pick up enough energy to ionize the lattice. The net result of this positive feedback mechanism is a rapid rise of IC, which puts the transistor out of useful (or controllable) range of operation. The VCE corresponding the rapid rise in IC is called the breakdown voltage. Collapse of Current Gain The breakdown voltage represents the absolute maximum bias that can be applied to a bipolar transistor. There is, in addition, one more physical phenomenon that further restricts VCE to values smaller than the breakdown voltage. This phenomenon occurs in multi-finger HBTs, having roots in the thermalelectrical interaction in the device. It is termed the collapse of current gain (or gain collapse) to emphasize the abrupt decrease of current gain observed in measured I-V characteristics when VCE increases past certain values. Figure 5.13 is one such example, measured from a 2-finger HBT. The figure reveals two distinct operating regions, separated by a dotted curve. When VCE is small, IC decreases gradually with VCE, exhibiting a negative differential resistance (NDR). We briefly describe the cause of NDR, as it relates to the understanding of the gain collapse. The band diagrams in Figs. 5.3 and 5.4 showed that the backinjected holes from the base into the emitter experience a larger energy barrier than the emitter electrons forward injected into the base. The ratio of the desirable IC to the undesirable IB,back-inject is proportional to exp(ΔEg /kT) in a graded HBT, and exp(ΔEv /kT) in an abrupt HBT. At room temperature, this ratio is large in either HBT. However, as VCE increases, the power dissipation in the HBT increases, gradually elevating the device temperature above the ambient temperature. IC /IB,back-inject, and hence the current gain, gradually decrease with increasing VCE. Since Fig. 5.13 is measured IC for several constant IB, the decreasing β directly translates to the gradual decrease of IC. As VCE crosses the dotted curve, NDR gives in to the collapse phenomenon, as marked by a dramatic lowering of IC. The collapse locus, the dotted curve, is the collection of IC as a function of VCE at which the gain collapse occurs. When several identical transistors are connected together to common emitter, base, and collector electrodes, we tend to expect each transistor to conduct the same amount of collector current for any biases. Contrary to our intuition, equal conduction takes place only when the power dissipation is low to moderate, such that the junction temperature rise above the ambient temperature is small. At high VCE and/or high IC operation where the transistor is operated at elevated temperatures, one transistor spontaneously starts to conduct more current than the others (even if all the transistors are ideal and identical). Eventually, one transistor conducts all the current while the others become electrically inactive. This current imbalance originates from a universal bipolar transistor property that as the junction temperature increases, the bias required to turn on some arbitrary current level decreases. Quantitatively, this property is expressed by an empirical expression relating IC, VBE, and T: (5.12) where IC,sat is the collector saturation current; VBE,junction is the bias across the base-emitter junction; T0 is the ambient temperature; and T is the actual device temperature. The degree of the turn-on voltage change in response to a junction temperature change is characterized by φ, which is called the thermalelectrical feedback coefficient. φ decreases logarithmically with , and can be approximately as 1.1 mV/°C. This means that when the junction temperature exceeds the ambient temperature by 1°C, turning on the same amount of IC requires 1.1 mV less of VBE,junction. A multi-finger HBT can be viewed as consisting of several identical sub-HBTs, with their respective emitter, base, and collector leads connected together. If one finger (i.e., one sub-HBT) becomes slightly warmer than the others, its base-emitter junction turn-on voltage becomes slightly lower. Consequently, this particular finger conducts more current for a given fixed base-emitter voltage. The increased collector current, in turn, increases the power dissipation in the junction, raising the junction temperature even further. The gain collapse occurs when the junction temperature in one finger of the entire device becomes much hotter than the rest of the fingers, so that the feedback action of increased collector current with junction temperature quickly leads to the fact that just one particular finger conducts the entire device current. Since the transition from uniform current conduction to one finger domination occurs suddenly, the surge in junction temperature in the conducting finger quickly lowers the overall device current gain. The fundamental cause of both NDR and collapse is the current gain lowering at elevated temperatures. Their difference, however, lies in the degree of temperature increase as VCE increases. In the NDR region, all fingers share relatively the same amount of current and the junction temperatures increase gradually with VCE. In contrast, in the collapse region, as the device power is entirely dissipated in one finger and the junction temperature rises sharply, the current gain suddenly plummets. The equation governing the collapse locus (per unit finger) is given by: (5.13) where Rth is the thermal resistance per finger and RE is the emitter resistance per finger. When the individual finger current is below this critical current level (or when IC,collapse is negative), all fingers share the same amount of current. Above this critical current level, one finger conducts most of the current, whereas the rest of the fingers share the remaining current equally. Equation (5.13) shows that an effective method to increase IC,collapse is to increase RE. The portion of the resistance that is intentionally introduced into device fabrication (such as by connecting a TaN thin-film resistor in series with the emitter electrode) is called the ballasting resistance. Alternatively, IC,collapse can be increased by reducing the thermal resistance, a goal often requiring more elaborate processes. Equation (5.13) neglects the contribution from the base resistance, RB. For III-V HBTs, it is actually advantageous to use base ballasting; i.e., with the ballasting resistance placed in the base terminal. The reason why the base ballasting approach is undesirable for Si BJT has been analyzed. The collapse of current gain occurring in III-V HBTs, closely relates to the thermal runaway in Si BJTs. HBTs suffering from gain collapse remain functional and can be biased out of the collapse region by reducing VCE. Si BJTs suffering from thermal runaway, however, die instantly. The bias conditions triggering the thermal runaway in Si BJTs are identically given by the collapse locus equation [Eq. (5.13)]. The main cause of the difference between the collapse in HBTs and thermal runaway in Si BJTs is that the current gain increases with temperature in Si BJTs whereas it decreases with temperature in HBTs. High Frequency Performance Current gain is the most important DC parameter characterizing a bipolar transistor. The high frequency properties are generally measured by two figures of merit: fT, the cutoff frequency, and fmax, the maximum oscillation frequency. The cutoff frequency is the frequency at which the magnitude of the AC current gain (small-signal collector current divided by small-signal base current) decreases to unity. As far as analytical expression is concerned, it is easier to work with the related emitter-collector transit time (τec), which is inversely proportional to fT : (5.14) The emitter-collector transit time can be broken up into several components. The emitter charging time, τe, is the time required to change the base potential by charging up the capacitances through the differential base-emitter junction resistance: (5.15) Cj,BE and Cj,BC denote the junction capacitances of the base-emitter and the base-collector junctions, respectively. The inverse dependence of τe on IC is the primary reason why BJTs and HBTs are biased at high current levels. When the current density is below 104 A/cm2, this term often dominates the overall collector-emitter transit time. The second component is the base transit time, the time required for the forward-injected charges to diffuse/drift through base. It is given by, (5.16) The value of ν depends on the magnitude of the base quasi-electric field. In a uniform base without a base field, ν is 2, as suggested by Eq. (5.8). Depending on the amount of energy-gap grading, ν can easily increase to 6 to 10. The space-charge transit time, τsc, is the time required for the electrons to drift through the depletion region of the base-collector junction. It is given by, (5.17) where Xdep is the depletion thickness of the base-collector junction. The factor of 2 results from averaging the sinusoidal of carriers current over a time period.3 It is assumed in the derivation that, because the electric field is large throughout the entire reverse-biased base-collector junction, the carriers travel at a constant saturation velocity, vsat. With a p– collector layer placed adjacent to the p+ base of an otherwise conventional Npn HBT,23 the electric field near the base can be made smaller than εcrit. Consequently, the electrons travel at the velocity determined completely by the Γ valley. Without scattering to the L valley, the electrons continue to travel at a velocity that is much larger than vsat, and τsc is significantly reduced. When carriers travel faster than vsat under an off-equilibrium condition, velocity overshoot is said to occur. The last term, the collector charging time, τc, is given by, (5.18) where RE and RC are the device emitter and collector resistances, respectively. The value of this charging time depends greatly on the parasitic resistances. This is the term that degrades the HBT's high frequency performance when the contacts are poorly fabricated. The overall transit time is a sum of the four time constants: (5.19) In most HBTs, RE and RC are dominated by the electrode resistances; the epitaxial resistances in the emitter and collector layers are insignificant. The cutoff frequency relates to τec through Eq. (5.14). The maximum oscillation frequency is the frequency at which the unilateral power gain is equal to 1. The derivation is quite involved,3 but the final result is elegant: (5.20) The base resistance has three components that are roughly equal in magnitude. They are base electrode resistance (RB,eltd); intrinsic base resistance (RB,intrinsic); and extrinsic base resistance (RB,extrinsic). RB,eltd is intimately related to processing, depending on the contact metal and the alloying recipe used to form the contact. The other two base resistance components, in contrast, depend purely on the designed base layer and the geometrical details. The HBT cross-sections illustrated in Fig. 5.8 show two base contacts placed symmetrically beside the central emitter mesa. For this popular transistor geometry, the intrinsic base resistance is given by, (5.21) where WE and LE are the emitter width and length, respectively; and RSH,base is the base sheet resistance in Ω/square. Where does the 1/12 factor come from? If all of the base current that goes into one of the base contacts in Fig. 5.8 leaves from the other contact, the intrinsic base resistance would follow our intuitive formula of simple resistance, equal to RSH,base × WE /LE. However, during the actual transistor operation, the base current enters through both contacts, but no current flows out at the other end. The holes constituting the base current gradually decrease in number as they are recombined at the extrinsic base surface, in the base bulk layer, and in the base-emitter space-charge region. Some base current carriers remain in the base layer for a longer portion of the width before getting recombined. Other carriers get recombined sooner. The factor 1/12 accounts for the distributed nature of the current conduction, as derived elsewhere.3 Because of the way the current flows in the base layer, the intrinsic base resistance is called a distributed resistance. If instead there is only one base contact, the factor 1/12 is replaced by 1/3 (not 1/6!).24 The distributed resistance also exists in the gate of MOS transistors,25 or III-V field-effect transistors. The extrinsic base resistance is the resistance associated with the base epitaxial layer between the emitter and the base contacts. It is given by, (5.22) where SBE is the separation between the base and emitter contacts. The factor 1/2 appears in the transistor shown in Fig. 5.8, which has two base contacts. The presence of RB,extrinsic is the reason why most transistors are fabricated with self-aligned base-emitter contacts, and that the base contacts are deposited right next to the emitter contacts, regardless of the finite alignment tolerance between the base and emitter contact photolithographical steps. (A detailed fabrication process will be described shortly.) With self-alignment, the distance SBE is minimized, to around 3000 Å. A detailed calculation of fT and fmax has been performed for a WE × LE = 2 × 30 μm2 HBT,4 with a SBE of 0.2 μm, a base thickness of 800 Å, a base sheet resistance of 280 Ω/square, and a base diffusion coefficient of 25.5 cm2/s. Although device parameters will have different values in other HBT structures and geometries, the exemplar calculation gives a good estimation of the relative magnitudes of various terms that determine a HBTs high frequency performance. We briefly list the key results here. The HBT has: RE = 0.45 Ω; RB,eltd = 7 Ω; RB,extrinsic = 0.94 Ω; RB,intrinsic = 1.56 Ω; Cj,BE = 0.224 pF; Cj,BC = 0.026 pF. It was further determined at the bias condition of JC = 104 A/cm2 and VBC = –4 V, that the collector depletion thickness Xdep = 0.59 μm. Therefore, Summing up these four components, we find the emitter-collector transit time to be 6.14 ps. The cutoff frequency is therefore 1/(2π·6.14 ps) = 26 GHz. As mentioned, although this calculation is specific to a particular power HBT design, the relative magnitudes of the four time constants are quite representative. Generally, the space-charge transit time is the major component of the overall transit time. This is unlike silicon BJTs, whose τb and τe usually dominate, because of the low base diffusion coefficient in the silicon material and the high base-emitter junction capacitance associated with high emitter doping. HBT design places a great emphasis on the collector design, while the Si BJT design concentrates on the base and emitter layers. The total base resistance is RB = 7 + 0.96 + 1.95 = 9.91 Ω. The maximum oscillation frequency, calculated with Eq. (5.20), is 65 GHz. Figure 5.14 illustrates the cutoff and maximum oscillation frequencies of a state-of-art InAlAs/InGaAs HBT. The frequency responses are plotted as a function of the collector current to facilitate the circuit design at the proper bias condition. When the current is small, the cutoff frequency is small because the emitter charging time is large. As the current increases, fT increases because the emitter charging time decreases. When the current density exceeds roughly 105 A/cm2, Kirk effects take place and the transistor performance degrades rapidly. fmax's current dependence follows fT's, as governed by the relationship of Eq. (5.20). The high frequency transistor of the calculated example has a narrow width of 2 μm. What happens if WE increases to a large value, such as 200 μm? A direct application of Eq. (5.19) would still lead to a cutoff frequency in the GHz range. In practice, such a 200 μm wide device will have a cutoff frequency much smaller than 1 GHz. The reason for the discrepancy is simple; the time constants appearing in Eq. (5.19), which all roughly scale with the emitter area, are based on the assumption that the current conduction is uniform within the entire emitter mesa. In HBTs, and more so in Si BJTs, the base resistance is significant. As the base current flows horizontally from the base contacts to the center of the emitter region, some finite voltage is developed, with a increasingly larger magnitude toward the center of the mesa. The effective base-emitter junction voltage is larger at the edge than at the center. Since the amount of carrier injection depends exponentially on the junction voltage at the given position, most of the injection takes place near the emitter edges, hence the term emitter crowding. Sometimes this phenomenon of nonuniform current conduction is referred to as the base crowding. Both terms are acceptable, depending on whether the focus is on the crowding of the emitter current or the base current. A figure of merit quantifying the severity of emitter crowding is the effective emitter width (Weff ). It is defined as the emitter width that would result in the same current level if current crowding were absent and the emitter current density were uniform at its edge value. Figure 5.15 illustrates the effective emitter width (normalized by the defined emitter width) as a function of base doping and collector current. Because of the emitter crowding, all high-frequency III-V HBTs capable of GHz performance have a narrow emitter width on the order of 2 μm. For wireless applications in the 2 GHz range, 2 to 3 μm WE is often used,26 but a 6.4 μm WE has also been reported.27 The choice of the emitter width is a trade-off between the ease (cost) of device fabrication versus the transistor performance. We intuitively expected the Weff /WE ratio to increase as the doping increased (since the base resistance decreased). However, an increase in base doping was accompanied by shortened minority lifetime. The large increase in IB,bulk causes the emitter crowding to be more pronounced as Nbase increases, as shown in Fig. 5.15. Due to differences in material properties, the emitter width in Si BJT or SiGe HBTs tends to be on the order of 0.5 μm. Device Fabrication An HBT mask layout suitable for high-frequency applications is shown in Fig. 5.16, and a corresponding fabrication process is delineated in Fig. 5.17. The following discussion of processing steps assumes the AlGaAs/GaAs HBT epitaxial structure shown in Fig. 5.6. The first step is to deposit ~7000 Å of silicon dioxide, onto which the first-mask pattern "ISOL" is defined, and 1.5 μm of aluminum, evaporated and lifted off. The aluminum protects the silicon dioxide underneath during the subsequent reactive ion etch (RIE), resulting in the profile shown in Fig. 5.17a. Oxygen atoms or protons are then implanted everywhere on the wafer. This implantation is designed to make the region outside of "ISOL" pattern electrically inactive. A shallow etching is applied right after the implantation so that a trail mark of the active device area is preserved. This facilitates the alignment of future mask levels to the first mask. Afterward, both aluminum and oxide are removed with wet etching solutions, reexposing the fresh InGaAs top surface onto which a refractory metal (such as W) is sputtered. The "EMIT" mask level is used to define the emitter mesas, and Ti/Al, a conventional contact metal used in III-V technologies, is evaporated and lifted off. If a refractory metal is not inserted between the InGaAs semiconductor and the Ti/Al metal, long-term reliability problems can arise as titanium reacts with indium. During the ensuing RIE, the refractory metal not protected by the emitter metal is removed. The resulting transistor profile is shown in Fig. 5.17b. Wet or dry etching techniques are applied to remove the exposed GaAs cap and the AlGaAs active emitter layer, and eventually reach the top of the base layer. Silicon nitride is deposited by plasma enhanced chemical vapor deposition (PECVD). This deposition is conformal, forming a nitride layer everywhere, including the vertical edges. Immediately after the nitride deposition, the whole wafer is etched by RIE. Because a vertical electric field is set up in the RIE chamber to propel the chemical species in the vertical direction, the sidewall nitride covering the sides of the emitter mesas remains untouched while the nitride layer lying on a flat surface is etched away (Fig. 5.17c). The nitride sidewall improves the device yield by cutting down the possible electrical short between the emitter contact and the soon-to-be-deposited base contacts. The step after the nitride sidewall formation is the "BASE" lithography. As shown in the layout of Fig. 5.16, there is no separation between the "BASE" and the "EMIT" levels. The base metal during the evaporation partly lands on the emitter mesa, and some of it lands on the base layer as desired (Fig. 5.17d). The process has the desired feature that, even if the "BASE" level is somewhat misaligned with the "EMIT" level, the distance SBE between the emitter and base contacts is unchanged, and is at the minimum value determined by the thickness of the nitride sidewall. In this manner, the base contact is said to be selfaligned to the emitter. Self-alignment reduces RB,extrinsic [Eq. 5.22)] and Cj,BC, hence improving the highfrequency performance. Typically, Ti/Pt/Au is the choice for the base metal. Following the base metal formation, the collector is defined and contact metal of Au/Ge/Ni/Au is deposited (Fig. 5.17e). After the contact is alloyed at ~450°C for ~1 minute, a polyimide layer is spun to planarize the device as shown in Fig. 5.17f. The contact holes are then defined and Ti/Au is evaporated to contact various electrodes. The final device cross-section after the entire process is shown in Fig. 5.17g. 6. Metal-Oxide-Semiconductor Field-Effect Transistors The insulated-gate field-effect transistor was conceived in the 1930s by Lilienfeld and Heil. An insulatedgate transistor is distinguished by the presence of an insulator between the main control terminal and the remainder of the device. Ideally, the transistor draws no current through its gate (in practice a small leakage current on the order of 10–18 A to 10–16A exists). This is in sharp contrast to bipolar junction transistors that require a significant base current to operate. Unfortunately, the Metal-Oxide-Semiconductor-Field-EffectTransistor (MOSFET) had to wait nearly 30 years until the 1960s when manufacturing advances made the device a practical reality. Since then, the explosive growth of MOSFET utilization in every aspect of electronics has been phenomenal. The use of MOSFETs in electronics became ever more prevalent when "complementary" types of MOSFET devices were combined by Wanlass in the early 1960s to produce logic that required virtually no power except when changing state. MOSFET processes that offer complementary types of transistors are known as Complementary Metal Oxide Semiconductor (CMOS) processes, and are the foundation of the modern commodity electronics industry. The MOSFET's primary advantages over other types of integrated devices are its mature fabrication technology, its high integration levels, its mixed analog/digital compatibility, its capability for low voltage operation, its successful scaling characteristics, and the combination of complementary MOSFETs yielding low power CMOS circuits. In this section, basic material concerning the MOSFET physical structure and operation is first presented. Nonideal effects are briefly discussed, as are important parasitics and distributed effects found in MOSFETs. Once the important parasitics and distributed effects are understood, the operation of MOSFETs at radio frequencies is examined, and important MOSFET operating parameters are given. Following this, MOSFET noise sources relevant to radio frequency designs are discussed. This section concludes with a discussion of MOSFET design and physical layout appropriate for radio frequency implementations. MOSFET Fundamentals Today, each of the tens of millions of MOSFETs that can occupy mere square centimetres of silicon area shares the same basic physical structure. The physical structure of the MOSFET is deceptively simple, as illustrated by the MOSFET cross-section appearing in Fig. 6.1. Visible in the figure are the various materials used to construct a MOSFET. These materials appear in layers when the MOSFET cross-section is viewed; this is a direct consequence of the processes of "doping," deposition, growth, and etching which are fundamental in conventional processing facilities. The fabrication process of silicon MOSFET devices has evolved over the last 30 years into a reliable integrated circuit manufacturing technology. Silicon has emerged as the material of choice for MOSFETs, largely because of its stable oxide, SiO2, which is used as a general insulator, as a surface passivation layer, and as an excellent gate dielectric. Full appreciation of the MOSFET structure and operation requires some knowledge of silicon semiconductor properties and "doping." These topics are briefly reviewed next. On the scale of conductivity that exists between pure insulators and perfect conductors, semiconductors fall between the extremes. The semiconductor material commonly used to make MOSFETs is silicon. Pure, or "intrinsic" silicon exists as an orderly three-dimensional array of atoms, arranged in a crystal lattice. The atoms of the lattice are bound together by covalent bonds containing silicon valence electrons. At absolute-zero temperature, all valence electrons are locked into these covalent bonds and are unavailable for current conduction, but as the temperature is increased, it is possible for an electron to gain enough thermal energy to escape its covalent bond, and in the process leave behind a covalent bond with a missing electron, or "hole." When that happens the electron that escaped is free to move about the crystal lattice. At the same time, another electron, which is still trapped in nearby covalent bonds because of its lower energy state, can move into the hole left by the escaping electron. The mechanism of current conduction in intrinsic silicon is therefore by hole-electron pair generation, and the subsequent motion of free electrons and holes throughout the lattice. At normal temperatures intrinsic silicon behaves as an insulator because the number of free electronhole pairs available for conducting current is very low, only about 14.5 hole-electron pairs per 1000 μm of silicon. The conductivity of silicon can be adjusted by adding foreign atoms to the silicon crystal. This process is called "doping," and a "doped" semiconductor is referred to as an "extrinsic" semiconductor. Depending on what type of material is added to the pure silicon, the resulting crystal structure can either have more electrons than the normal number needed for perfect bonding within the silicon structure, or less electrons than needed for perfect bonding. When the dopant material increases the number of free electrons in the silicon crystal, the dopant is called a "donor." The donor materials commonly used to dope silicon are phosphorus, arsenic, and antimony. In a donor-doped semiconductor the number of free electrons is much larger than the number of holes, and so the free electrons are called the "majority carriers" and the holes are called the "minority carriers." Since electrons carry a negative charge and they are the majority carriers in a donor-doped silicon semiconductor; any semiconductor that is predominantly doped with donor impurities is known as "n-type." Semiconductors with extremely high donor doping concentrations are often denoted "n+ type." Dopant atoms that accept electrons from the silicon lattice are also used to alter the electrical characteristics of silicon semiconductors. These types of dopants are known as "acceptors." The introduction of the acceptor impurity atoms creates the situation in which the dopant atoms have one less valence electron than necessary for complete bonding with neighboring silicon atoms. The number of holes in the lattice therefore increases. The holes are therefore the majority carriers and the electrons are the minority carriers. Semiconductors doped with acceptor impurities are known as "p-type," since the majority carriers effectively carry a positive charge. Semiconductors with extremely high acceptor doping concentrations are called "p+ type." Typical acceptor materials used to dope silicon are boron, gallium, and indium. A general point that can be made concerning doping of semiconductor materials is that the greater the dopant concentration, the greater the conductivity of the doped semiconductor. A second general point that can be made about semiconductor doping is that n-type material exhibits a greater conductivity than p-type material of the same doping level. The reason for this is that electron mobility within the crystal lattice is greater than hole mobility, for the same doping concentration. MOSFET Physical Structure and Operation A cross-section through a typical n-type MOSFET, or "NFET," is shown in Fig. 6.2(a). The MOSFET consists of two highly conductive regions (the "source" and the "drain") separated by a semiconducting channel. The channel is typically rectangular, with an associated length (L) and width (W). The ratio of the channel width to the channel length, W/L, is an important determining factor for MOSFET performance. As shown in Fig. 6.2(a), the MOSFET is considered a four-terminal device. These terminals are known as the gate (G), the bulk (B), the drain (D), and the source (S), and the voltages present at these terminals collectively control the current that flows within the device. For most circuit designs, the current flow from drain to source is the desired controlled quantity. The operation of field-effect transistors (FETs) is based upon the principal of capacitively controlled conductivity in a channel. The MOSFET gate terminal sits on top of the channel, and is separated from the channel by an insulating layer of SiO2. The controlling capacitance in a MOSFET device is therefore due to the insulating oxide layer between the gate and the semiconductor surface of the channel. The conductivity of the channel region is controlled by the voltage applied across the gate oxide and channel region to the bulk material under the channel. The resulting electric field causes the redistribution of holes and electrons within the channel. For example, when a positive voltage is applied to the gate, it is possible that enough electrons are attracted to the region under the gate oxide, that this region experiences a local inversion of the majority carrier type. Although the bulk material is p-type (the majority carriers are holes and minority carriers are electrons), if enough electrons are attracted to the same region within the semiconductor material, the region becomes effectively n-type. Then the electrons are the majority carriers and the holes are the minority carriers. Under this condition electrons can flow from the n+ type drain to the n+ type source if a sufficient potential difference exists between the drain and source. When the gate-to-source voltage exceeds a certain threshold, called VT , the conductivity of the channel increases to the point where current may easily flow between the drain and the source. The value of VT required for this to happen is determined largely by the dopant concentrations in the channel, but it also depends in part upon the voltage present on the bulk. This dependence of the threshold voltage upon the bulk voltage is known as the "body effect." In MOSFETs, both holes and electrons can be used for conduction. As shown in Fig. 6.2, both n-type and p-type MOSFETs are possible. If, for an n-type MOSFET, all the n-type regions are replaced with p-type regions and all the p-type regions are replaced with n-type regions, the result is a p-type MOSFET. Since both the n-type and p-type MOSFETs require substrate material of the opposite type of doping, two distinct CMOS technologies exist, defined by whether the bulk is n-type or p-type. If the bulk material is p-type substrate, then n-type MOSFETs can be built directly on the substrate while p-type MOSFETs must be placed in an n-well. This type of process is illustrated in Fig. 6.2(a). Another possibility is that the bulk is composed of n-type substrate material, and in this case the p-type MOSFETs can be constructed directly on the bulk, while the n-type MOSFETs must be placed in an p-well, as in Fig. 6.2(b). A third type of process known as twin-well or twin-tub CMOS requires that both the p-type and n-type MOSFETs be placed in wells of the opposite type of doping. Other combinations of substrate doping and well types are in common use. For example, some processes offer a "deep-well" capability, which is useful for threshold adjustments and circuitry isolation. Modern MOSFETs differ in an important respect from their counterparts developed in the 1960s. While the gate material used in the field effect transistors produced thirty years ago was made of metal, the use of this material was problematic for several reasons. At that time, the gate material was typically aluminium and was normally deposited by evaporating an aluminium wire by placing it in contact with a heated tungsten filament. Unfortunately, this method led to sodium ion contamination in the gate oxide, which caused the MOSFET's threshold voltage to be both high and unstable. A second problem with the earlier methods of gate deposition was that the gate was not necessarily correctly aligned with the source and drain regions. Matching between transistors was then problematic because of variability in the gate location with respect to source and drain for the various devices. Parasitics also varied greatly between devices because of this variability in gate location with respect to the source and drain regions. In the worst case, a nonfunctional device was produced because of the errors associated with the gate placement. Devices manufactured today employ a different gate material, namely "polysilicon," and the processing stages used to produce a field-effect transistor with a poly gate are different than the processing stages required to produce a field-effect transistor with a metal gate. In particular, the drain and source wells are patterned using the gate and field oxide as a mask during the doping stage. Since the drain and source regions are defined in terms of the gate region, the source and drain are automatically aligned with the gate. CMOS manufacturing processes are referred to as self-aligning processes when this technique is used. Certain parasitics, such as the overlap parasitics considered later in this chapter, are minimized using this method. The use of a polysilicon gate tends to simplify the manufacturing process, reduces the variability in the threshold voltage, and has the additional benefit of automatically aligning the gate material with the edges of the source and drain regions. The use of polysilicon for the gate material has one important drawback: the sheet resistance of polysilicon is much larger than that of aluminium and so the resistance of the gate is larger when polysilicon is used as the gate material. High-speed digital processes require fast switching time from the MOSFETs used in the digital circuitry, yet a large gate resistance hampers the switching speed of a MOSFET. One method commonly used to lower the gate resistance is to add a layer of silicide on top of the gate material. A silicide is a compound formed using silicon and a refractory metal, for example TiSi2. Later in this chapter the importance of the gate resistance upon the radio frequency performance of the MOSFET is examined. In general, the use of silicided gates is required for reasonable radio frequency MOSFET performance. Although the metal-oxide-semiconductor sandwich is no longer regularly used at the gate, the devices are still called MOSFETs. The term Insulated-Gate-Field-EffectTransistor (IGFET) is also in commonusage. MOSFET Large Signal Current-Voltage Characteristics When a bias voltage in excess of the threshold voltage is applied to the gate material, a sufficient number of charge carriers are concentrated under the gate oxide such that conduction between the source and drain is possible. Recall that the majority carrier component of the channel current is composed of charge carriers of the type opposite that of the substrate. If the substrate is p-type silicon then the majority carriers are electrons. For n-type silicon substrates, holes are the majority carriers. The threshold voltage of a MOSFET depends on several transistor properties such as the gate material, the oxide thickness, and the silicon doping levels. The threshold voltage is also dependent upon any fixed charge present between the gate material and the gate oxides. MOSFETs used in most commodity products are normally the "enhancement mode" type. Enhancement mode n-type MOSFETs have a positive threshold voltage and do not conduct appreciable charge between the source and the drain unless the threshold voltage is exceeded. In contrast, "depletion mode" MOSFETs exhibit a negative threshold voltage and are normally conductive. Similarly, there exists enhancement mode and depletion mode p-type MOSFETs. For p-type MOSFETs the sign of the threshold voltage is reversed. Equations that describe how MOSFET threshold voltage is affected by substrate doping, source and substrate biasing, oxide thickness, gate material, and surface charge density have been derived in the literature. Of particular importance is the increase in the threshold voltage associated with a nonzero source-to bulk voltage. This is known as the "body effect" and is quantified by the equation, (6.1) Where VT0 is the zero-bias threshold voltage, γ is the body effect coefficient or body factor, φF is the bulk surface potential, and VSB is the bulk-to-source voltage. Details on the calculation of each of the terms in Eq. (6.1) is discussed extensively in the literature. Operating Regions MOSFETs exhibit fairly distinct regions of operation depending upon their biasing conditions. In the simplest treatments of MOSFETs, the three operating regions considered are subthreshold, triode, and saturation. Subthreshold When the applied gate-to-source voltage is below the device's threshold voltage, the MOSFET is said to be operating in the subthreshold region. For gate voltages below the threshold voltage, the current decreases exponentially toward zero according to the equation (6.2) Where n is given by (6.3) in which γ is the body factor, φj is the channel junction built-in voltage, and vBS is the source-to-bulk voltage. For radio frequency applications, the MOSFET is normally operated in its saturation region. The reasons for this will become clear later in this section. It should be noted, however, that some researchers feel that it may be advantageous to operate deep-submicron radio frequency MOSFETs in the moderate inversion (subthreshold) region. Triode — A MOSFET operates in its triode, also called "linear" region, when bias conditions cause the induced channel to extend from the source to the drain. When VGS>VT the surface under the oxide is inverted and if VDS> 0 a drift current will flow from the drain to the source. The drain-to-source voltage is assumed small so that the depletion layer is approximately constant along the length of the channel. Under these conditions, the drain source current for an NMOS device is given by the relation, (6.4) where μn is the electron mobility in the channel and C′ox is the per unit area capacitance over the gate area. Similarly, for PMOS transistors the current relationship is given as, in which the threshold voltage of the p-type MOSFET is assumed to be positive and μp is the hole mobility. Saturation — The conditions VD≤VGS –VT in Eq. (6.4) and VSD≤VSG – VT in Eq. (6.5) ensure that the inversion charge is never zero for any point along the channel's length. However, when VDS= VGS–VT (or VSD= VSG – VT in PMOS devices) the inversion charge under the gate at the channel-drain junction is zero. The required drain-to-source voltage is called VDS,sat for NMOS and VSD,sat for PMOS. For VDS > VDS,sat (VSD > VSD,sat for PMOS), the channel charge becomes "pinched off," and any increase in VDS increases the drain current only slightly. The reason that the drain currents will increase for increasing VDS is because the depletion layer width increases for increasing VDS. This effect is called channel length modulation and is accounted for by λ, the channel length modulation parameter. The channel length modulation parameter ranges from approximately 0.1 for short channel devices to 0.01 for long channel devices. Since MOSFETs designed for radio frequency operation normally use minimum channel lengths, channel length modulation is an important concern for radio frequency implementations in CMOS. When a MOSFET is operated with its channel pinched off, in other words VDS > VGS – VT and VGS ≥ VT for NMOS (or VSD > VSG – VT and VSG ≥ VT for PMOS), the device is said to be operating in the saturation region. The corresponding equations for the drain current are given by, (6.6) for long-channel NMOS devices and by, (6.7) for long-channel PMOS devices. Figure 6.3 illustrates a family of curves typically used to visualize a MOSFET's drain current as a function of its terminal voltages. The drain-to-source voltage spans the operating region while the gateto- source voltage is fixed at several values. The bulk-to source voltage has been taken as zero. As shown in Fig. 6.3, when the MOSFET enters the saturation region the drain current is essentially independent of the drain-to-source voltage and so the curve is flat. The slope is not identically zero however, as the drain-to-source voltage does have some effect upon the channel current due to channel modulation effects. Three simplifying assumptions are advantageous when one is trying to gain an intuitive understanding of the low-frequency operation of a circuit containing MOSFETs. When operated in the linear region, the MOSFET can be treated much like a resistor with terminal voltage VDS. When operated in the saturation region, the MOSFET may be considered a voltage-controlled current source where the controlling voltage is present at the gate. Finally, when operated below the voltage threshold, the MOSFET can be considered an open circuit from the drain to the source. Nonideal and Short Channel Effects The equations presented for the subthreshold, triode, and saturation regions of the MOSFET operating characteristic curves do not include the many nonidealities exhibited by MOSFETs. Most of these nonideal behaviors are more pronounced in deep submicron devices such as those employed in radio frequency designs, and so it is important for a designer to be aware of them. Velocity saturation — Electron and hole mobility are not constants; they are a function of the applied electric field. Above a certain critical electric field strength the mobility starts to decrease, and the drift velocity of carriers does not increase in proportion to the applied electric field. Under these conditions the device is said to be velocity saturated. Velocity saturation has important practical consequences in terms of the current-voltage characteristics of a MOSFET acting in the saturation region. In particular, the drain current of a velocity saturated MOSFET operating in the saturation region is a linear function of VGS. This is in contrast to the results given in Eqs. (6.6) and (6.7). The drain current for a short channel device operating under velocity saturation conditions is given by Drain-induced barrier lowering — A positive voltage applied to the drain terminal helps to attract electrons under the gate oxide region. This increases the surface potential and causes a threshold voltage reduction. Since the threshold decreases with increasing VDS, the result is an increase in drain current and therefore an effective decrease in the MOSFET's output resistance. The effects of draininduced barrier lowering are reduced in modern CMOS processes by using lightly doped drain (LDD) structures. Hot carriers — Velocity saturated charge carriers are often called hot carriers. Hot carriers can potentially tunnel through the gate oxide and cause a gate current, or they may become trapped in the gate oxide. Hot carriers that become trapped in the gate oxide change the device threshold voltage. Over time, if enough hot carriers accumulate in the gate oxide, the threshold voltage is adjusted to the point that analog circuitry performance is severely degraded. Therefore, depending upon the application, it may be unwise to operate a device so that the carriers are velocity saturated since the reliability and lifespan of the circuit is degraded. Small Signal Models Small signal equivalent circuits are useful when the voltage and current waveforms in a circuit can be decomposed into a constant level plus a small time-varying offset. Under these conditions, a circuit can be linearized about its DC operating point. Nonlinear components are replaced with linear components that reflect the bias conditions. The low-frequency small signal model for a MOSFET is shown in Fig. 6.4. Only the intrinsic portion of the transistor is considered for simplicity. As shown, the small signal model consists of three components: the small signal gate transconductance, gm; the small signal substrate transconductance, gmb; and the small signal drain, gd. Mathematically, these three components are defined by, (6.9) (6.10) and (6.11) Equations (6.9), (6.10), and (6.11) can be evaluated using the relationships given earlier. For the saturation region, the small signal transconductances and the drain conductance are given by, (6.12) (6.13) and (6.14) where η in Eq. (6.13) is a factor that describes how the threshold voltages changes with reverse body bias. For small VBS, η ≈ 0. The small signal model shown in Fig. 6.4 is only valid at very low frequencies. At higher frequencies capacitances present in the MOSFET must be included in the small signal model, and at radio frequencies distributed effects must be taken into account. In the next section these two factors are explored and the small signal model is revised. CMOS at Radio Frequencies Integrated radio frequency transceiver design is an evolving field, particularly in terms of understanding device performance and maximizing integration level. Typical commercial implementations of highlyintegrated high-performance wireless transceivers use a mixture of technologies, including CMOS, BiCMOS, BJTs, GaAs FETs, and HBTs. Regardless of the technology, all radio frequency integrated circuits contend with the same issues of noise, linearity, gain, and efficiency. The best technology choice for an integrated radio frequency application must weigh the consequences of wafer cost, level of integration, performance, economics, and time to market. These requirements often lead designers into using several technologies within one transceiver system. Partitioning of transceiver functionality according to technology implies that the signal must go on-chip and off-chip at several locations. Bringing the signal off-chip and then on-chip again complicates the transceiver design because proper matching at the output and input terminals is required. Also, bringing the signal off-chip implies that power requirements are increased because it takes more power to drive an off-chip load than to keep the signal completely on the same integrated circuit. Generally, taking the signal off and then on-chip results in signal power loss accompanied by an undesirable increase in noise figure. Recent trends apply CMOS to virtually the entire transceiver design, since CMOS excels in its level of integration. The level of integration offered by a particular technology determines the required die size, which in turn affects both the cost and the physical size of the final packaged circuitry. CMOS technology currently has the performance levels necessary to operate in the 900 MHz to 2.4 GHz frequency range, which is important for existing cellular and wireless network applications. Upcoming technologies should be able to operate in the 5 GHz ISM band, which is seen as the next important commodity frequency. CMOS devices manufactured with gate lengths of 0.18 μm will function at these frequencies, albeit with generous biasing currents. Future generations of CMOS scaled below the 100 nm gate length range are anticipated to provide the performance required to operate beyond the 5 GHz frequency range for receiver applications. High Frequency Modeling The majority of existing analog MOSFET models predate the use of CMOS in radio frequency designs and generally are unable to predict the performance of MOSFETs operating at microwave frequencies with the accuracy required and expected of modern simulators. These modeling shortcomings occur on two fronts. In the first case, existing models do not properly account for the distributed nature of the MOSFET, meaning that at high frequencies, geometry-related effects are ignored. In the second case, existing models do not properly model MOSFET noise at high frequencies. Typical problems with noise modeling include: • not accounting for velocity-saturated carriers within the channel and the associated noise; • discounting the significant thermal noise generated by the distributed gate resistance; • ignoring the correlation between the induced gate noise and the MOSFET drain noise. Accurate noise modeling is extremely important when low noise operation is essential, such as in a frontend low noise amplifier. High Frequency Operation MOSFET dimensions and physical layout are important determining factors for high frequency performance. As MOSFET operating frequencies approach several hundred MHz, the MOSFET can no longer be considered a lumped device. The intrinsic and extrinsic capacitance, conductance, and resistance are all distributed according to the geometry and physical layout of the MOSFET. The distributed nature of the MOSFET operating at high frequencies is particularly important for the front-end circuitry in a receiver, such as in the low noise amplifier and first stage mixer input MOSFETs. The devices used in these portions of the input circuitry are normally large, with high W/L ratios. Large W/L ratios are required because of the inherently low transconductance offered by CMOS, and in order to realize reasonable gain, the devices are therefore relatively wide compared to more conventional analog circuit layouts. Additionally, minimum gate lengths are preferred because the maximum operating frequency of the MOSFET scales as 1/L2. Shorter channels imply higher frequency because the time it takes the carriers to move from drain to source is inversely proportional to the length of the channel. Also, the mobility of the carriers is proportional to the electric field strength. Since the electric field strength along the length of the channel is inversely proportional to the distance between the source and the drain, the carrier mobility is inversely proportional to the length of the channel. Combined, these two effects have traditionally allowed the maximum operating frequency of the MOSFET to scale as 1/L2. It must be noted that in modern deep submicrometer MOSFETs experiencing velocity saturation, the maximum operating frequency no longer scales as 1/L2, but more closely to 1/L. In any event, for maximum operating frequency, the device channel length should be the minimum allowable. Since the gate width in RF front-end MOSFET devices is typically on the order of several hundred microns, the gate acts as a transmission line along its width. The gate acting as a transmission line is modeled similarly to a microstrip transmission line and can be analyzed by utilizing a distributed circuit model for transmission lines. Normally a transmission line is viewed as a two-port network in which the transmission line receives power from the source at the input port (source end) and delivers the power to the load of the output port (load end). In order to apply transmission line analysis to the gate of a MOSFET along its width, the width of the MOSFET gate is divided into many identical sections of incremental width Δx. Each portion of the transmission line with the width Δx is modeled by a resistance "R" per unit width, an inductance "L" per unit width, a capacitance "C" per unit width, and a conductance "G" per unit width. Normally the transmission line is assumed to be uniform, so that these parameters are constants along the transmission line's width. When analyzing signal propagation along the MOSFET gate width, it is important to note that there is no single output node. The transmission line cannot be treated as a two-port, since the gate couples to the channel in a distributed fashion. Important Parasitics and Distributed Effects Parasitic capacitances — At high operating frequencies the effects of parasitic capacitances on the operation of the MOSFET cannot be ignored. Transistor parasitic capacitances are subdivided into two general categories; extrinsic capacitances and intrinsic capacitances. The extrinsic capacitances are associated with regions of the transistor outside the dashed line shown in Fig. 6.5, while the intrinsic capacitances are all those capacitances located within the region illustrated in Fig. 6.5. Extrinsic capacitances — Extrinsic capacitances are modeled by using small-signal lumped capacitances, each of which is associated with a region of the transistor's geometry. Seven small-signal capacitances are used, one capacitor between each pair of transistor terminals, plus an additional capacitor between the well and the bulk if the transistor is fabricated in a well. Figure 6.6(a) illustrates the seven extrinsic transistor capacitances added to an intrinsic small signal model, and Fig. 6.6(b) assigns a location to each capacitance within the transistor structure. In order of importance to high frequency performance, the extrinsic capacitances are as follows: Gate overlap capacitances — Although MOSFETs are manufactured using a self-aligned process, there is still some overlap between the gate and the source and the gate and the drain. This overlapped area gives rise to the gate overlap capacitances denoted by CGSO and CGDO for the gate-to-source overlap capacitance and the gate-to-drain overlap capacitance, respectively. Both capacitances CGSO and CGDO are proportional to the width, W, of the device and the amount that the gate overlaps the source and the drain, typically denoted as "LD" in SPICE parameter files. The overlap capacitances of the source and the drain are often modeled as linear parallel plate capacitors, since the high dopant concentration in the source and drain regions and the gate material implies that the resulting capacitance is largely bias independent. However, for MOSFETs constructed with a lightly doped drain (LDD-MOSFET), the overlap capacitances can be highly bias dependent and therefore nonlinear. For a treatment of overlap capacitances in LDD-MOSFETs, refer to Klein.7 For non-lightly doped drain MOSFETs, the gate-drain and gate-source overlap capacitances are given by the expression CGSO = CGDO = W LD Cox, where Cox is the thin oxide field capacitance per unit area under the gate region. When the overlap distances are small, fringing field lines add significantly to the total capacitance. Since the exact calculation of the fringing capacitance requires an accurate knowledge of the drain and source region geometry, estimates of the fringing field capacitances based on measurements are normally used. Extrinsic junction capacitances — The bias-dependent junction capacitances that must be considered when evaluating the extrinsic lumped-capacitance values are illustrated in Fig. 6.6(a) and summarized in Table 6.1. At the source region there is a source-to-bulk junction capacitance, CjBS,e, and at the drain region there is a drain-to-bulk junction capacitance, CjBD,e. These capacitances can be calculated by splitting the drain and source regions into a "side wall" portion and a "bottom wall" portion. The capacitance associated with the side wall portion is found by multiplying the length of the side wall perimeter (excluding the side contacting the channel) by the effective side wall capacitance per unit length. Similarly, the capacitance for the bottom wall portion is found by multiplying the area of the bottom wall by the bottom wall capacitance per unit area. Additionally, if the MOSFET is in a well, a well-to-bulk junction capacitance, CjBW,e, must be added. The well-bulk junction capacitance is calculated similar to the source and drain junction capacitances, by dividing the total well-bulk junction capacitance into side wall and bottom wall components. If more than one transistor is placed in a well, the well-bulk junction capacitance should only be included once in the total model. Both the effective side wall capacitance and the effective bottom wall capacitance are bias dependent. Normally the per unit length zero-bias, side wall capacitance and the per unit area zero-bias, bottom wall capacitance are estimated from measured data. The values of these parameters for nonzero reversebias conditions are then calculated using the formulas given in Table 6.1. Extrinsic source-drain capacitance — Accurate models of short channel devices may include the capacitance that exists between the source and drain region of the MOSFET. As shown in Fig. 6.6(a), the source-drain capacitance is denoted as Csd,e. Although the source-drain capacitance originates in the region within the dashed line in Fig. 6.5, it is still referred to as an extrinsic capacitance.1 The value of this capacitance is difficult to calculate because its value is highly dependent upon the source and drain geometries. For longer channel devices, Csd,e is very small in comparison to the other extrinsic capacitances, and is therefore normally ignored. Extrinsic gate-bulk capacitance — As with the gate-to-source and gate-to-drain overlap capacitances, there is a gate-to-bulk overlap capacitance caused by imperfect processing of the MOSFET. The parasitic gate-bulk capacitance, CGB,e, is located in the overlap region between the gate and the substrate (or well) material outside the channel region. The parasitic extrinsic gate-bulk capacitance is extremely small in comparison to the other parasitic capacitances. In particular, it is negligible in comparison to the intrinsic gate-bulk capacitance. The parasitic extrinsic gate-bulk capacitance has little effect on the gate input impedance and is therefore generally ignored in most models. Intrinsic capacitances — Intrinsic MOSFET capacitances are significantly more complicated than extrinsic capacitances because they are a strong function of the voltages at the terminals and the field distributions within the device. Although intrinsic MOSFET capacitances are distributed throughout the device, for the purposes of simpler modeling and simulation, the distributed capacitances are normally represented by lumped terminal capacitances. The terminal capacitances are derived by considering the change in charge associated with each terminal with respect to a change in voltage at another terminal, under the condition that the voltage at all other terminals is constant. The five intrinsic small signal capacitances are therefore expressed as, These capacitances are evaluated in terms of the region of operation of the MOSFET, which is a function of the terminal voltages. Detailed models for each region of operation were investigated by Cobbold. Simplified expressions are given in Table 6.2, for the triode and saturation operating regions. The total terminal capacitances are then given by combining the extrinsic capacitances and intrinsic capacitances according to, in which the small-signal form of each capacitance has been used. The contribution of the total gate-to-channel capacitance, CGC, to the gate-to-drain and gate-to-source capacitances is dependent upon the operating region of the MOSFET. The total value of the gate-tochannel capacitance is determined by the per unit area capacitance Cox and the effective area over which the capacitance is taken. Since the extrinsic overlap capacitances include some of the region under the gate, this region must be removed when calculating the gate-to-channel capacitance. The effective channel length, Leff , is given by Leff = L – 2LD so that the gate-to-channel capacitance can be calculated by the formula CGC = CoxW Leff . The total value of the gate-to-channel capacitance is apportioned to both the drain and source terminals according to the operating region of the device. When the device is in the triode region, the capacitance exists solely between the gate and the channel and extends from the drain to the source. Its value is therefore evenly split between the terminal capacitances Cgs and Cgd as shown in Table 6.2. When the device operates in the saturation region, the channel does not extend all the way from the source to the drain. No portion of CGC is added to the drain terminal capacitance under these circumstances. Again, as shown in Table 6.2, analytical calculations demonstrated that an appropriate amount of CGS to include in the source terminal capacitance is 2/3 of the total. Finally, the channel to bulk junction capacitance, CBC, should be considered. This particular capacitance is calculated in the same manner as the gate-to-channel capacitance. Also similar to the gate-to-channel capacitance proportioning between the drain in the source when calculating the terminal capacitances, the channel-to-bulk junction capacitance is also proportioned between the source-to-bulk and drain-tobulk terminal capacitances, depending on the region of operation of the MOSFET. Wiring capacitances — Referring to Fig. 6.1, one can see that the drain contact interconnect overlapping the field oxide and substrate body forms a capacitor. The value of this overlap capacitance is determined by the overlapping area, the fringing field, and the oxide thickness. Reduction of the overlapping area will decrease the capacitance to a point, but with an undesirable increase in the parasitic resistance at the interconnect to MOSFET drain juncture. The parasitic capacitance occurring at the drain is particularly troublesome due to the Miller effect, which effectively magnifies the parasitic capacitance value by the gain of the device. The interconnects between MOSFET devices also add parasitic capacitive loads to the each device. These interconnects may extend across the width of the IC in the worst case, and must be considered when determining the overall circuit performance. Modern CMOS processes employ thick field-oxides that reduce the parasitic capacitance that exists at the drain and source contacts, and between interconnect wiring and the substrate. The thick field-oxide also aids in reducing the possibility of unintentional MOSFET operation in the field region. Distributed gate resistance — Low-frequency MOSFET models treat the gate as purely capacitive. This assumption is invalid for frequencies beyond approximately 1 GHz, because the distributed gate resistance is typically larger than the capacitive reactance present at the gate input for frequencies beyond 1 GHz. The impact of the distributed gate resistance upon the high frequency performance of MOSFETs has been investigated both experimentally and analytically by several researchers.1,6,9–15 The distributed gate resistance affects the radio frequency performance of the MOSFET in three primary ways. In the first case, discounting the gate resistance causes nonoptimal power matching to off-chip source impedances. In the second case, discounting the distributed gate resistance in noise figure calculations causes an underestimation of the noise figure of the transistor. Finally, in the third case, since the power gain of the MOS transistor is strongly governed by the gate resistance, discounting the gate resistance causes an overestimation of the MOSFET's available power gain and maximum oscillation frequency. The gate resistance of MOSFET transistors therefore deserves important consideration during the design phase of integrated RF CMOS receivers. Nonzero gate resistances have been factored into recent successful designs. Rofougaran et al.16 noted that matching, input noise, and voltage gain are all ultimately limited by transistor imperfections such as gate resistance. The effects were most recently quantified by Enz. Channel charging resistance — Charge carriers located in the channel cannot instantaneously respond to changes in the MOSFET gate-to-source voltage. The channel charging resistance is used to account for this non-quasi-static behavior along the channel length. In Bagheri et al.,15 the channel charging resistance was shown to be inversely proportional to the MOSFET transconductance, ri ≈ (kgm)–1. For long channel devices, with the distributed nature of the channel resistance between the source and drain taken into account, the constant of proportionality, k, was shown to equal five. Measurements of short channel devices indicate that the proportionality constant can go as low as one. The channel charging resistance of a MOSFET is important because it strongly influences the input conductance and the forward transconductance parameters of the device. Both the input conductance and the forward transconductance are monotonically decreasing functions of the channel charging resistance. Since the transconductance of even a large MOSFET is small, on the order of 10 mS, the charging resistance of typical front-end transistors is large, potentially on the order of hundreds of ohms. Transconductance delay — MOSFET transconductance does not respond instantaneously to changes in gate voltage. The time it takes for the charge in the channel to be redistributed after an excitation of the gate voltage is dictated by the time constant due to the gate-to-source capacitance and the channel charging resistance. This time constant is denoted as τ, and is given by the expression τ ≈ riCgs. The transconductance delay is generally ignored for frequencies less than 2π/τ. Small Signal Models — Several high frequency small signal models incorporating the effects described in the previous sections have been proposed in the literature. The small signal model presented in Fig. 6.7 is useful for MOSFETs operating in saturation in a common-source configuration. Evident in the figure are the various lumped terminal capacitances, the drain conductance, and the output transconductance. Note that the transconductance gmb is taken as zero because VSB = 0 is assumed. Also evident in the model are the high-frequency related elements, the namely the charging resistance, the transconductance delay, and the extrinsic and intrinsic gate resistances. MOSFET Small Signal Y-parameters Small-signal y-parameters are useful in radio frequency design work involving MOSFETs. As discussed later in this section, radio frequency MOSFETs are typically laid out in a "fingered" style, and if the y-parameters are found for a single finger, they are easily combined for the complete device. The y-parameters corresponding to the small signal equivalent circuit shown in Fig. 6.7 have been evaluated and appear in Table 6.3. These y-parameters cannot accurately portray the distributed nature of the MOSFET at high frequencies because the model presented in Fig. 6.7 is composed of lumped elements. Recall that the gate resistance in MOS transistors operating at GHz frequencies in conjunction with intrinsic and extrinsic device capacitances acts as a distributed RC network. This is shown schematically in Fig. 6.8, where a MOSFET is represented as a network of smaller MOSFETs, interconnected by gate material. Several models developed over the last three decades incorporate high frequency and distributed effects. Noise arising from the distributed gate was modeled by Jindal,12 but high frequency effects were not incorporated in this model. Distributed geometry effects were recognized as important,14,15 but the distributed nature of the gate was not fully explored analytically.10 As the viability of CMOS in RF transceiver applications improved, significant progress in modeling wide devices, such as those required for RF applications, was made by Kim et al.11 and Razavi et al.,9 in which wide transistors were treated as arrays of smaller transistors interconnected by resistors representing the gate. Recently in a paper by Abou-Allam,17,18 a closed-form, small signal model incorporating the distributed gate for wide transistors was derived, taking into account the distributed nature of the gate resistance and intrinsic capacitances. The y-parameters developed in Abou-Allam's paper17 appear here in Table 6.3. A parallel between the results presented by Razavi et al.9 and Abou-Allam18 was drawn in a paper by Tin et al.,19 in which a useful small signal lumped circuit model was presented and leads to the model here in Fig. 6.9. The lumped model shown in Fig. 6.9 incorporates the distributed effects represented by the tanh(γW)/γW factor within the expressions for the y-parameters presented in Table 6.3. The distributed gate resistance appears as a lumped resistor of value Rg /3 and the distributed intrinsic capacitances appear as a lumped capacitor with value Cg/5. It is important to note that these expressions were derived for a gate connected from one end only. For example, when the gate is connected from both ends, the equivalent resistor changes to Rg /12. The performance limitations imposed by distributed effects at radio frequencies was summarized by Manku. Analysis of a two-port constructed from the y-parameters as given in Table 6.3 for a traditional MOSFET yields several important device performance metrics, as now discussed. Unity Current Gain Frequency: ft The unity current gain frequency is defined as the signal input frequency at which the extrapolated smallsignal current gain of the MOSFET equals one. The small-signal current gain is defined as the amplitude of the small-signal drain current to the small-signal gate current. The symbol used in the literature to denote the unity current gain frequency is ft and is read as the "transit frequency." The unity current gain frequency, or transit frequency, is used as a benchmark to describe the speed of the intrinsic device. The performance of the complete device, which includes the additional effects of the extrinsic parasitics, is always lower. For linear amplifier configurations, the small-signal unity current gain is of primary concern since it determines the maximum achievable gain-bandwidth product of the amplifier. Small signal linear two-port models are useful for estimating the unity current gain frequency. The value of ft is most easily found from the y-parameters using the relation, were derived for a gate connected from one end only. For example, when the gate is connected from both ends, the equivalent resistor changes to Rg /12. The performance limitations imposed by distributed effects at radio frequencies was summarized by Manku. Analysis of a two-port constructed from the y-parameters as given in Table 6.3 for a traditional MOSFET yields several important device performance metrics, as now discussed. Unity Current Gain Frequency: ft The unity current gain frequency is defined as the signal input frequency at which the extrapolated smallsignal current gain of the MOSFET equals one. The small-signal current gain is defined as the amplitude of the small-signal drain current to the small-signal gate current. The symbol used in the literature to denote the unity current gain frequency is ft and is read as the "transit frequency." The unity current gain frequency, or transit frequency, is used as a benchmark to describe the speed of the intrinsic device. The performance of the complete device, which includes the additional effects of the extrinsic parasitics, is always lower. For linear amplifier configurations, the small-signal unity current gain is of primary concern since it determines the maximum achievable gain-bandwidth product of the amplifier. Small signal linear two-port models are useful for estimating the unity current gain frequency. The value of ft is most easily found from the y-parameters using the relation, (6.21) which holds when the current gain is unity. From y-parameters given in Table 6.3, the value of ft is found as, (6.22) where Cg2 - (gmRgiCgs – Cgs)2 is assumed. Note that the unity current gain frequency is independent of the distributed gate resistance. The most important determining factors of the unity current gain frequency are the device transconductance and the gate-to-source and gate-to-drain capacitances. Since the device ft is directly proportional to gm, the analog circuit designer can trade power for speed by increasing the device bias current and therefore gm. Note that ft cannot be arbitrarily increased by an increase in drain-source bias current; eventually gm becomes independent of IDS, and therefore ft becomes independent of the bias current. MOSFETs used at radio frequencies are normally operated in saturation, because gm is maximum for a given device in the saturation region. Recall that gm can also be increased by increasing the width of the transistor, but this will not increase ft because the parasitic capacitance Cg is proportional to the width of the device. The transit frequency must not be confused with another often used performance metric, the "intrinsic cutoff frequency," fτ. While both the "t" in ft and the "τ" in fτ refer to the carrier transit time along the length of the device channel, the two symbols have decidedly different meanings. The intrinsic cutoff frequency is given by where τ is the mean transit time of the carriers along the channel length. Typically, fτ is five or six times larger than ft. Maximum Available Power Gain: Gmax Maximum port-to-po rt power gain within a device occurs when both the input and the output ports are matched to the impedance of the source and the load, respectively. The maximum available power gain of a device, Gmax, provides a fundamental limit on how much power gain can be achieved with the device. The maximum available power gain achievable within a linear two-port network can be described in terms of the two-port y-parameters as, (6.23) where the two-port system is assumed to be unconditionally stable. Treating a common-source MOSFET as a two-port and using the y-parameters shown in Table 6.3 and the relation for ft given in Eq. (6.22), the MOSFET Gmax is derived in terms of the intrinsic device parameters as, (6.24) in which the simplifying assumption (Rg,i + ri)gds _ gmRg,iCgd /Cg is made. To first order, the maximum achievable power gain of a MOSFET is proportional to the device's ft, and the maximum achievable power gain is inversely proportional to the device's intrinsic gate resistance, Rg,i. Note that linear amplification is assumed in Eqs. (6.23) and (6.24). Equation (6.24) therefore applies to small-signal analyses such as for a receiver front-end, and would possibly be inadequate for describing the maximum power gain achievable using a nonlinear power amplifier in the transmitter portion of a transceiver. Unity Power Gain Frequency: fmax The third important figure of merit for MOSFET transistors operating at radio frequencies is the maximum frequency of oscillation, fmax. This is the frequency at which the maximum available power gain of the transistor is equal to one. An estimate of fmax for MOSFET transistors operating in saturation is found from Eq. (6.24) by setting Gmax = 1 and is given by, (6.25) From a designer's perspective, fmax can be optimized by a combination of proper device layout and careful choice of the operating bias point. From Eq. (6.22) ft ∝ gm, therefore fmax ∝ , and hence gm should be maximized. Maximizing gm requires some combination of increasing the gate-source overdrive, increasing device bias current IDS, or increasing the device width. Note that increasing the device width will increase Rg,i and reduce fmax unless a fingered layout is used. 7. Metal Semiconductor Field Effect Transistors Silicon Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) dominate modern microelectronics. Gallium Arsenide Metal Semiconductor Field Effect Transistors (GaAs MESFETs) are "runnersup," and they find many important niche applications in high-speed or high frequency circuits. After the first successful fabrication of GaAs MESFETs by Mead in 1966 and after the demonstration of their performance at microwave frequencies in 1967 by Hooper and Lehrer, these devices emerged as contenders with silicon MOSFETs and bipolar transistors. In the late 1970s and early 1980s, high quality semi-insulating substrates and ion-implantation processing techniques made it possible to fabricate GaAs MESFET VLSI circuits, such as 16×16 multipliers with a multiplication time of 10.5 ns and less than 1 W power dissipation. Today GaAs MESFETs play an important role in both analog and digital applications, such as for satellite and fiber-optic communication systems, in cellular phones, in automatic IC test equipment, and for other civilian and military uses. The microwave performance of GaAs MESFETs approaches that of Heterostructure Field Effect Transistors (HFETs). As discussed below, the record maximum frequency of oscillations and the record cutoff frequency, fT, for GaAs MESFETs reached 190 and 168 GHz, respectively. Even though the record numbers of fmax and fT for GaAs- and InP-based HFETs reach 400 GHz and 275 GHz, respectively, their more typical fmax and fT are well within the reach of GaAs MESFET technology. The integration scale of GaAs MESFET integrated circuits approaches 1,000,000 transistors. Emerging materials for MESFET applications are SiC and GaN wide bandgap semiconductors that have a much higher breakdown voltage, a higher thermal conductivity, and a higher electron velocity than GaAs. SiC MESFETs are predicted to reach breakdown voltages up to nearly 100 kV. However, SiGe and even advanced, deep submicron Si technologies emerge as a serious competitor to GaAs MESFET technology at relatively low frequencies (below 40 GHz or so). This trend toward SiGe and Si might be alleviated by a shift toward 150 mm GaAs substrates, which are now used by the leading GaAs IC manufacturers, such as Vitesse, Anadigics, Infinion, Motorola, Tektronix, and RFMD. In this section, we first discuss the MESFET principles of operation. Then we review the material properties of semiconductors competing for applications in MESFETs and the properties of Schottky barrier contacts followed by a brief review of MESFET fabrication, and MESFET modeling. We also consider wide bandgap semiconductor MESFETs, new emerging hetero-dimensional MESFETs, and discuss applications of the MESFET technology. Principle of Operation Figure 7.1 shows a schematic MESFET structure. In n-channel MESFETs, an n-type channel connects n+ drain and source regions. The depletion layer under the Schottky barrier gate contact constricts the current flow across the channel between the source and drain. The gate bias changes the depletion region thickness, and, hence, modulates the channel conductivity. This device is very different from a silicon Metal Oxide Semiconductor Field Effect Transistor (MOSFET), where a silicon dioxide layer separates the gate from the channel. MOSFETs are mainstream devices in silicon technology, and silicon MESFETs are not common. Compound semiconductors, such as GaAs, do not have a stable oxide, and a Schottky gate allows one to avoid problems related to traps in the gate insulator, such as hot electron trapping in the gate insulator, threshold voltage shift due to charge trapped in the gate insulator, and so on. In normally-off (enhancement mode) MESFETs, the channel is totally depleted by the gate built-in potential even at zero gate voltage (see Fig. 7.2). The threshold voltage of normally-off devices is positive. In normally-on (depletion mode) MESFETs, the conducting channel has a finite cross-section at zerogate voltage. The drawback of normally-off MESFET technology is a limited gate voltage swing due to the low turn-on voltage of the Schottky gate. This limitation is much less important in depletion mode FETs with a negative threshold voltage. Also, this limitation is less important in low power digital circuits operating with a low supply voltage. Usually, the source is grounded, and the drain is biased positively. A schematic diagram of the depletion region under the gate of a MESFET for a finite drain-to-source voltage is shown in Fig. 7.3. The depletion region is wider closer to the drain because the positive drain voltage provides an additional reverse bias across the channel-to-gate junction. With an increase in the drain-to-source bias, the channel at the drain side of the gate becomes more and more constricted. Finally, the velocity of electrons saturates leading to the current saturation (see Fig. 7.4 that shows typical MESFET currentvoltage characteristics). MESFETs have been fabricated using many different semiconductor materials. However, GaAs MESFETs are mainstream MESFET devices. In many cases, GaAs MESFETs are fabricated by direct ion implantation into a GaAs semi-insulating substrate, making GaAs IC fabrication less complicated than silicon CMOS fabrication. Properties of Semiconductor Materials Used in MESFET Technology The effective mass of electrons in GaAs is very small (0.067me in GaAs compared to 0.98 me longitudinal effective mass and 0.19 me transverse effective mass in Si, where me is the free electron mass). This leads to a much higher electron mobility in GaAs — approximately 8500 cm2/Vs in pure GaAs at room temperature compared to 1500 cm2/Vs in Si. As shown in Fig. 7.5, the electron velocity in GaAs exceeds that for the electrons in Si. This is an important advantage for modern day short channel devices, where the electric fields are higher than the peak velocity field under normal operating conditions. The light electrons in GaAs also experience so-called overshoot or even ballistic transport in short channel devices, where the electron transit time becomes comparable to or even smaller than the electron energy or even momentum relaxation time. This boosts the electron velocity well above the expected steady-state values (see Fig. 7.6). GaN also has a high electron velocity and pronounced overshoot effects (see Figs. 7.5 and 7.6). Another important advantage of GaAs and related compound semiconductors is the availability of semi-insulating material that could serve as a substrate for device and circuit fabrication. A typical resistivity of semi-insulating GaAs is 100 MΩ -cm or larger, compared to 2.5×105Ω-cm for intrinsic silicon at room temperature. The semi-insulating GaAs is used as a substrate for fabricating GaAs MESFETs and other devices. Passive elements can also be fabricated on the same substrate, which is a big advantage for fabricating Monolithic Microwave Integrated Circuits (MMICs). As mentioned above, an important advantage of the GaAs MESFET is the possibility of fabricating these devices and integrated circuits using a direct implantation into the semi-insulating GaAs substrate. Since GaAs, InP, and related semiconducting materials are direct gap materials, they are widely used in optoelectronic applications. Hence, electronic and photonic devices can be integrated on the same chip for use in optical interconnects or in optoelectronic circuits. The direct band gap leads to a high recombination rate, which improves radiation hardness. GaAsbased devices can survive over 100 megarads of ionizing radiation. as power devices (because of a small intrinsic carrier concentration and a high breakdown field). Table 7.1 summarizes important material properties of semiconductors used in MESFET technology. Schottky Barrier Contacts Figure 7.7 shows the energy band diagram of a GaAs Schottky barrier metal-semiconductor contact at zero bias. The Fermi level will be constant throughout the entire metal-semiconductor system, and the energy band diagram in the semiconductor is similar to that for an n-type semiconductor in a p+ -n junction. Energies Φm and Φs shown in Figure 7.7 are called the metal and the semiconductor work functions. The work function is equal to the difference between the vacuum level (which is defined as a free electron energy in vacuum) and the Fermi level. The electron affinity of the semiconductor, Χs (also shown in Fig. 7.7), corresponds to the energy separation between the vacuum level and the conduction band edge of the semiconductor. In the idealized picture of the Schottky junction shown in Fig. 7.7, the energy barrier between the semiconductor and the metal is (7.1) Here Χs is the electron affinity in the semiconductor, Φs and Φm are the metal work functions, and φb is the Schottky barrier height, q is the electronic charge [in Eq. (7.1) and in Fig. 7.7, φb is measured in eV, and Φs and Φm are measured in Joules). Since Φm > Φs the metal is charged negatively. The positive net space charge in the semiconductor leads to a band bending (7.2) Where Vbi is called the built-in voltage, in analogy with the corresponding quantity in a p-n junction. Equation (7.1) and Fig. 7.7 are not quite correct. In reality, a change in the metal work function, Φm, is not equal to the corresponding change in the barrier height, φb, as predicted by Eq. (7.1). In actual Schottky diodes, φb increases with an increase in Φm, but only by 0.1 to 0.3 eV when Φm increases by 1 to 2 eV. This difference is caused by interface states and is determined by the properties of a thin interfacial layer. However, even though a detailed and accurate understanding of Schottky barrier formation remains a challenge, many properties of Schottky barriers may be understood independently of the exact mechanism determining the barrier height. In other words, we can simply determine the effective barrier height from experimental data. A forward bias decreases the potential barrier for electrons moving from the semiconductor into the metal and leads to an exponential rise in current. At high forward biases (approaching the built-in voltage), the voltage drop across the series resistance (comprised of the contact resistance and the resistance of the neutral region between the ohmic contact and the depletion region) becomes important, and the overall current-voltage characteristic of a Schottky diode can be described by the following diode equation (7.3) where Is is the saturation current, Rs is the series resistance, Vth = kBT/q is the thermal voltage, η is the ideality factor (η typically varies from 1.02 to 1.6), q is the electronic charge, kB is the Boltzmann constant, and T is temperature. The diode saturation current, Is, is typically much larger for Schottky barrier diodes than in p-n junction diodes since the Schottky barrier height is smaller than the barrier height in p-n junction diodes. For a p-n junction, the height of the barrier separating electrons in the conduction band of the n-type region from the bottom of the conduction band in the p-region is on the order of the energy gap. The current mechanism in Schottky diodes depends on the doping level. In a relatively low-doped semiconductor, the depletion region between the semiconductor and the metal is very wide, and electrons can only reach the metal by going over the barrier. In higher doped samples, the barrier near the top is narrow enough for the electrons to tunnel through. Finally, in very highly doped structures, the barrier is thin enough for tunneling at the Fermi level. Figure 7.8 shows the band diagrams illustrating these three conduction mechanisms. For low-doped devices, the saturation current density, jss, in a Schottky diode is given by where A* is called the Richardson constant, T is temperature (in degrees Kelvin), and kB is the Boltzmann constant. For a conduction band minimum with the spherical surface of equal energy (such as the Γ minimum in GaAs), (7.5) where mn is the effective mass, me is the free electron mass, h is the Planck constant, and α is an empirical factor on the order of unity. The Schottky diode model described by Eqs. (7.4) and (7.5) is called the thermionic emission model. For Schottky barrier diodes fabricated on the {111} surfaces of Si, A* = 96 A/(cm2K2). For GaAs, A∗ = 4.4 A/(cm2K2). As stated above, in higher doped semiconductors, the depletion region becomes so narrow that electrons can tunnel through the barrier near the top. This conduction mechanism is called thermionicfield emission. The current-voltage characteristic of a Schottky diode in the case of thermionic-field emission (i.e., for higher doped semiconductors) under forward bias is given by: (7.6) where (7.7) (7.8) (7.9) Here Ec is the bottom of the conduction band in a semiconductor (outside of the depletion region and EFn is the electron quasi-Fermi level. In GaAs Schottky diodes, the thermionic-field emission becomes important for Nd > 1017 cm–3 at 300 K and for Nd > 1016 cm–3 at 77 K. In silicon, the corresponding values of Nd are several times larger. In degenerate semiconductors, especially in semiconductors with a small electron-effective mass, such as GaAs, electrons can tunnel through the barrier near or at the Fermi level, and the tunneling current is dominant. This mechanism is called field emission. The resistance of the Schottky barrier in the field emission regime is quite low. Metal-n+ contacts operated in this regime are used as ohmic contacts. Figure 7.9 shows a small signal equivalent circuit of a Schottky diode, which includes a parallel combination of the differential resistance of the Schottky barrier (7.10) and the differential capacitance of the space charge region: (7.11) Here V and I are the voltage drop across the Schottky diode and the current flowing through the Schottky diode, respectively, Vbi is the built-in voltage of the Schottky barrier, and Nd is the ionized donor concentration in the semiconductor. The equivalent circuit also includes the series resistance, Rs, which accounts for the contact resistance and the resistance of the neutral semiconductor region between the ohmic contact and the depletion region, the equivalent series inductance, Ls, and the device geometric capacitance: (7.12) where L is the device length and S is the device cross-section. MESFET Technology The most popular MESFETs (GaAs MESFETs) found in applications in both analog microwave circuits (including applications in Microwave Monolithic Integrated Circuits) and in digital integrated circuits. Ion implanted GaAs MESFETs represent the dominant technology for applications in digital integrated circuits. They also have microwave applications. Figure 7.10 shows a typical process sequence for ion implanted GaAs MESFETs (developed in late 1970s). In a typical fabrication process, a GaAs semi-insulating substrate is coated with a thin silicon nitride (Si3N4) film. Implantation steps shown in Fig. 7.10 are carried out through this layer. As shown in Fig. 7.10, the first implant defines the active layer including the MESFET channel. A deeper and a higher dose implant is used for ohmic contacts. This implant is often done as a self-aligned implant. In this case, a temperature-stable refractory metal-silicide gate (typically tungsten silicide) is used as a mask for implanting the n+ source and drain contacts. This technique reduces parasitic resistances. Also, this fabrication process is planar. However, the n+ implant straggle under the gate might increase gate leakage current and also cause carrier injection into the substrate.18 After the implants, an additional insulator is deposited in order to cap the GaAs surface for the subsequent annealing step. This annealing (at 800°C or above) activates the implants. For microwave applications, the devices are often grown by molecular beam epitaxy. In this design, a top of n+ layer doping extending from the source and drain contacts helps minimize the series resistances. Figure 7.11 shows the recessed gate MESFET structure, where the thickness of the active layer under the gate is reduced. A thick n-doped layer between the gate and the source and drain contacts leads to a relatively low series source and drain resistances. The position and the shape of the recess are very important, since they strongly affect the electric field distribution and the device breakdown voltage. In power devices, the gate contact in the recess is usually closer to the source than to the drain (see Fig. 7.12). Such placement reduces the source parasitic resistance and enhances the drain-source breakdown voltage by allowing additional expansion space for the high-field region at the drain side of the gate. Another important issue is the reduction of the gate series resistance. This can be achieved by using a T-shape gate or a so-called mushroom gate (which might be obtained by side etching the gate), see Fig. 7.13. In this design, the gate series resistance is reduced without an increase in the gate length, which determines the device cutoff frequency. MESFETs are usually passivated by a Si3N4 layer. This passivation affects the surface states and the surface depletion layer, and stress-related and piezoelectric effects can lead to shifts in the threshold voltage. Wide band gap semiconductors, such as SiC, GaN, and related materials, might potentially compete with GaAs for applications in MESFETs and other solid-state devices (see Fig. 7.14). SiC exists in more than 170 polytypes. The three most important polytypes are hexagonal 6H (α-SiC) and 4H, and cubic 3C (β-SiC). As stated in Table 7.1, SiC has the electron saturation drift velocity of 2 ×10^7 cm/s (approximately twice that of silicon), a breakdown field larger than 2,500 to 5,000 kV/cm (compared to 300 kV/cm for silicon), and a high thermal conductivity of 4.9 W/cm°C (compared to 1.3 W/cm°C for silicon and 0.5 W/cm°C for GaAs). These properties make SiC important for potential applications in high-power, high frequency devices as well as in devices operating at high temperatures and/or in harsh environments. Palmour et al.23 reported operation of α-SiC MESFETs at a temperature of 773°K. In a 6H-SiC MESFET fabricated by CREE (gate length 24 μm, channel depth 600 nm, doping 6.5 × 10^16 cm–3), the room temperature transconductance was approximately 4 mS/mm. At elevated temperatures, the device transconductance decreases owing to the decrease in mobility. MESFETs did not exhibit breakdown even with drain voltages up to 100 V. Using the square law MESFET model (described below), Kelner and Shur24 estimated that the field effect mobility in these MESFETs was approximately 300 cm2/Vs. β-SiC. MESFETs have also been fabricated25 but α-SiC MESFETs exhibit better performance because of better material quality. α-SiC MESFETs have achieved microwave operation.26 A cutoff frequency of 5 GHz, 12 dB gain at 2 GHz, and a breakdown voltage of 200 V was demonstrated in an α-SiC MESFET with a 0.4 μm gate length. GaN is another material that is potentially important for MESFET applications. For GaN at room temperature and with an n-type doping density of 1017 cm–3, Monte Carlo simulations predict a high peak velocity (2.7 × 105 m/s), a high saturation velocity (1.5 × 105 m/s), and a high electron mobility (1000 cm2/Vs).28–31 Khan et al.32 and Binari et al.33 reported on microwave performance of GaN MESFETs. However, most of the research on GaN-based FETs has concentrated on GaN-based Heterostructure Field Effect Transistors. 7.6 MESFET Modeling MESFET modeling has been done at several different levels. Most advanced numerical simulation techniques rely on self-consistent simulation based on the Monte Carlo approach. In this approach, random number generators are used to simulate random electron scattering processes. The motion of these electrons is simulated in the electric field that is calculated self-consistently by solving the Poisson equation iteratively. The particle movements between scattering events are described by the laws of classical mechanics, while the probabilities of the various scattering processes and the associated transition rates are derived from quantum mechanical calculations. Self-consistent Monte Carlo simulations are very useful for revealing the device physics and verifying novel device concepts and ideas. A less rigorous, but also less numerically demanding approach relies on solving the balance equations. These partial differential equations describe conservation laws derived from the Boltzmann Transport Equation. Two-dimensional device simulators based on the balance equations and on the driftdiffusion model can be used to optimize device design and link the device characteristics to the device fabrication process. A more simplistic and easier approach is to use conventional drift-diffusion equations implemented in commercial two-dimensional and three-dimensional device simulators, such as ATLAS or MEDICI. However, even this approach might be too complicated and too numerically involved for the simulation of MESFET-based digital VLSI and/or for the simulation of MESFET-based analog circuits. The simplest model that relates the MESFET current-voltage characteristics to the electron mobility, the electron saturation velocity, the device dimensions, and applied voltages is called the square-law model. This model predicts the following equation for the drain saturation current: (7.13) where (7.14) is the transconductance parameter, (7.15) is the threshold voltage, VGS is the intrinsic gate-to-source voltage, and (7.16) is the pinch-off voltage. Here A is the channel thickness, μn is a low field mobility, and vs is the electron saturation velocity. This "square law" model is fairly accurate for devices with relatively low pinch-off voltages (Vpo = Vbi – VT ≤ 1.5 ~ 2 V). For devices with higher pinch-off voltages, the model called the Raytheon model (which is implemented in many versions of SPICE) yields a better agreement with experimental data: 7.17 Here tc is an empirical parameter that depends on the doping profile in the MESFET channel. Another empirical model (called the Sakurai-Newton model) is also quite useful for MESFET modeling: (7.18) The advantage of this model is simplicity. The disadvantage is that the empirical parameters βsn and msn cannot be directly related to the device and material parameters. (The Sakurai-Newton model is implemented in several versions of SPICE. In AIM-Spice,49,50 this model is implemented as Level 6 MOSFET model.) The source and drain series resistances, RS and Rd, may play an important role in determining the current-voltage characteristics of GaAs MESFETs. The intrinsic gate-to-source voltage, VGS, is given by (7.19) where Vgs is the applied (extrinsic) gate-to-source voltage. Substituting Eq. (7.19) into Eq. (7.16) and solving for Isat we obtain (7.20) In device modeling suitable for computer-aided design, one has to model the current-voltage characteristics in the entire range of drain-to-source voltages, not only in the saturation regime. In 1980, Curtice proposed the use of a hyperbolic tangent function for the interpolation of MESFET current-voltage characteristics (7.21) where (7.22) is the MESFET conductance at low drain-to-source voltages, and (7.23) is the intrinsic channel conductance at low drain-to-source voltages predicted by the Shockley model. The constant λ in Eq. (7.21) is an empirical constant that accounts for the output conductance in the saturation regime. This output conductance may be related to short channel effects and also to parasitic leakage currents in the substrate. Hence, output conductance may be reduced by using a heterojunction buffer layer between the device channel and the substrate or by using a p-type buffer layer. Such a layer creates an additional barrier, which prevents carrier injection into the substrate.18 The Curtice model is implemented in PSpice™. The Curtice model and the Raytheon model [see Eq. (7.23)] have become the most popular models used for MESFET circuit modeling. A more sophisticated model, which describes both subthreshold and above-threshold regimes of MESFET operation, is implemented in AIM-Spice. This model accurately reproduces current-voltage characteristics over several decades of currents and is suitable for both analog and digital circuit simulations.51 One of the simulation results obtained using this model is depicted in Fig. 7.15. In order to simulate MESFET circuits, one also needs to have a model describing the MESFET capacitances. Meyer53 proposed a simple charge-control model, in which capacitances (Cij = Cji) were obtained as derivatives of the gate charge with respect to the various terminal voltages. approximated a unified gate-channel capacitance Cgc of a MESFET at zero drain-source bias by the following combination of the above-threshold capacitance Ca and the below-threshold capacitance Cb: (7.24) This approach in conjunction with Meyer's model, leads to the following expressions for the gate-to-source (Cgs) and gate-to-drain capacitance (Cgd) valid for the sub-threshold and the above-threshold regimes: (7.25) (7.26) Here, Vsat is the extrinsic saturation voltage and Vdse is an effective extrinsic drain-source voltage that equals Vds for Vds < Vsat and Vsat for Vds > Vsat. A more accurate model of the intrinsic capacitances requires an analysis of the variation of the charge distribution in the channel versus terminal bias voltages. For the MESFET, the depletion charge under the gate has to be partitioned between the source and drain terminals. Finally, the gate leakage current has to be modeled in order to accurately reproduce MESFET current voltage characteristics in the entire range of bias voltages including positive gate biases. To a first order approximation, the gate leakage current can be described in terms of simple diode equations assuming that each "diode" represents half of the gate area: (7.27) Here L and W are the gate length and width, respectively, Jss is the saturation current, Vgs and Vgd are gate-to-source and gate-to-drain voltages, Vth is the thermal voltage, and mgs and mgd are the ideality factors. Figure 7.16 shows a more accurate equivalent circuit, which accounts for the effect of the leakage current on the drain current. In the equivalent circuit shown in Fig. 7.16, this effect is accounted for by the current controlled current source, Icorr . Here, Jss is the reverse saturation current density, and mgs and mgd are the gate-source and gate-drain ideality factors, respectively. A more accurate description proposed by Berroth et al.55 introduced effective electron temperatures at the source side and the drain side of the channel. The electron temperature at the source side of the channel Ts is taken to be close to the lattice temperature, and the drain side electron temperature Td is assumed to increase with the drain-source voltage to reflect the heating of the electrons in this part of the channel. The resulting gate leakage current can be written as (7.28) where Jgs and Jgd are the reverse saturation current densities for the gate-source and the gate-drain diodes, respectively, and Vths = kBTs/q and Vthd = kBTd /q. The second term in Eq. (7.28) accounts for the gate-drain leakage current and for the fact that the effective temperature of the electrons in the metal is maintained at the ambient temperature. In GaAs MESFETs, the reverse gate saturation current is usually also dependent on the reverse bias.56 The following expression accounts for this dependence: (7.29) where ggs and ggd are the reverse diode conductances and δg is the reverse bias conductance parameter. However, using the above expressions directly will cause a kink in the gate current and a discontinuity in its derivatives at zero applied voltage. Equation (7.29) is valid for both negative and positive values of Vgs and Vgd. Figure 7.17 compares the measured gate leakage current with the model implemented in AIM-Spice and described above.6 Figure 7.18 shows that the GaAs MESFET model implemented in AIM-Spice accurately reproduces the differential characteristics of the devices. Therefore, this model is suitable for the simulations of analog, microwave, and mixed-mode circuits. Applications GaAs MESFETs play an important role in both analog and digital applications, such as in satellite and fiber-optic communication systems, in cellular phones and other wireless equipment, in automatic IC test equipment, and for other diverse civilian and military uses. GaAs MESFETs have been used in highly efficient microwave power amplifiers, since they combine low on resistance and high cutoff frequency. GaAs semi-insulating substrates also present a major advantage for microwave applications, since they decrease parasitic capacitance and allow for fabrication of passive elements with low parasitics for microwave monolithic integration. GaAs MESFETs have also found applications in linear low-noise amplifiers. Figure 7.24 compares the cutoff frequencies and maximum frequencies of oscillations for different GaAs technologies. As can be seen from the figure, GaAs MESFETs exhibit quite respectable microwave performance and, given a lower cost of GaAs MESFETs compared to more advanced hetero-structure devices, they could capture a sizeable portion of the microwave market. GaAs MESFET technology has also been used in efficient DC-to-DC converters that demonstrated a high switching speed. These devices are capable of operating at a higher switching speeds and require a less complex circuitry. Vitesse Semiconductor Corporation is one of the leaders in digital GaAs MESFET technology. VSC8141 and the VSC8144 SONET/SDH OC-48 multi-rate transceivers include multiplexer and demultiplexer with integrated clock generation capabilities for the physical layer. Both ICs dissipate the lowest power available in the industry today. These integrated circuits are suitable for transmission systems, optical networking equipment, networking and digital cross-connect systems, and they have 20% lower power dissipation than competing products. High Electron Mobility Transistors (HEMTs) The concept of modulation doping was first introduced in 1978. In this technique electrons from remote donors in a higher bandgap material transfer to an adjacent lower gap material. The electrostatics of the heterojunction results in the formation of a triangular well at the interface, which confines the electrons in a two-dimensional (2D) electron gas (2DEG). The separation of the 2DEG from the ionized donors significantly reduces ionized impurity scattering resulting in high electron mobility and saturation velocity. Modulation-doped field effect transistors (MODFETs) or high electron mobility transistors (HEMTs), which use the 2DEG as the current conducting channel have proved to be excellent candidates for microwave and millimeter-wave analog applications and high-speed digital applications. This progress has been enabled by advances in crystal growth techniques such as molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD) and advances in device processing techniques, most notably electron beam lithography, which has enabled the fabrication of HEMTs with gate lengths down to 0.05 μm. formance. It is crucial to understand the principles of device operation and to take into consideration the effect of scaling to design a microwave or millimeter-wave HEMT device. The advantages and limitations of the material system used to implement the device also need to be considered. This section therefore begins with a discussion on the device operation of a HEMT. This is followed by a discussion of scaling issues in HEMT, which are of prime importance, as the reduction of gate length is required to increase the operating frequency of the device. The first HEMT was demonstrated in the AlGaAs/GaAs material system in 1981. It demonstrated significant performance improvements over the GaAs MESFET at microwave frequencies. However, the high-frequency performance was not sufficient for operation at millimeter-wave frequencies. In the past twenty years, the AlGaAs/InGaAs psuedomorphic HEMT on GaAs substrate (referred to as GaAs pHEMT) and the AlInAs/GaInAs HEMT on InP substrate (referred to as InP HEMT) have emerged as premier devices for microwave and millimeter-wave circuit applications. This highlights the importance of choosing the appropriate material system for device implementation. This will be discussed in the section on Material Systems for HEMT Devices. The next two sections will discuss the major advances in the development of the GaAs pHEMT and InP HEMT. Traditionally these devices have been used in low-volume, high-performance and high-cost military and space-based electronic systems. Recently the phenomenal growth of commercial wireless and optical fiber-based communication systems has opened up new applications for these devices. This also means that new issues like manufacturability and operation at low bias voltage have to be addressed. HEMT Device Operation and Design Linear Charge Control Model The current control mechanism in the HEMT is control of the 2DEG density at the heterojunction interface by the gate voltage. Figure 8.1 shows the band diagram along the direction perpendicular to the heterojunction interface using the AlGaAs/GaAs interface as an example. The first HEMT charge control model was proposed by Delagebeaudeuf and Linh in 1982. The potential well at the AlGaAs/GaAs interface is approximated by a triangular well. The energy levels in this triangular well and the maximum 2DEG density, nsm can be calculated by solving the Schrödinger equation in the triangular well and Poisson equation in AlGaAs donor layers. For 0 <ns<nsm, the sheet charge density ns as a function of gate voltage Vg can be expressed as (8.1) Where Cs is the 2DEG capacitance per unit area and is given by the following expression: (8.2) Here Δd is the distance of the centroid of the 2DEG distribution from the AlGaAs/GaAs interface and is typically or the order of 80 Å for ns~ 10^12/cm2. Here Vth is the threshold voltage or pinch-off voltage and is given by, (8.3) Where φb, ND, and dnare the Schottky barrier height on the donor layer, doping density, and doped layer thickness as illustrated in Fig. 8.1. Here, ΔEF is the Fermi potential of the 2DEG with respect to the bottom of the conduction band. It can be expressed as a function of 2DEG density as follows (8.4) Where ΔEFO(T) = 0 at 300 K, a= 0.125 × 10^–16 V/m^2 . This simplified version of charge control is accurate only at low temperature. At room temperature, apart from the 2DEG charge density ns, the gate voltage also modulates the bound carrier density, nbound in the donor layer and the free electrons, nfree in the donor layers. This results in premature saturation of the sheet charge and degradation of device performance. A more accurate model for charge control, which solves Poisson's and Schrödinger's equations in a self-consistent manner was proposed by Vinter. Modulation Efficiency The parasitic modulation of charge in the higher bandgap donor layer reduces the efficiency of the gate voltage to modulate the drain current, as the carriers in the donor layers do not contribute the drain current. The modulation efficiency (η) of the FET is proportional to ratio between the change in drain current (δ Ids) and the change in total charge (δQtot) required to cause this change. This ratio is defined as follows, (8.5) Dividing the numerator and denominator by the change in gate voltage, δVg that is required to cause this change, the following expression is obtained, (8.6) The modulation efficiency is defined as the ratio of the rate of change of the useful charge, i.e., the 2DEG over that of the total charge, (8.7) The relation between the modulation efficiency and high frequency performance of the FET is evident in the expressions for transconductance (gm) and current gain cutoff frequency (fT). (8.8) Hence, to improve the high frequency performance it is essential to improve the modulation efficiency. Equation (8.8) must be used with caution in case of short gate length HEMTs. The saturation velocity vsat may be replaced by the effective velocity veff. Usually Veff is higher than vsat due to high field and velocity overshoot effects. Using vsat in this case may lead to values of modulation efficiency that are greater than 100%. Current-Voltage (I-V) Models for HEMTs By assuming linear charge control, gradual channel approximation, and a 2-piece linear velocity-field model, the expression for the saturated drain current IDSS in a HEMT is given by, (8.9) Here Ec is defined as the critical electric field at which the electrons reach their saturation velocity vsat and Vc(0) is the channel potential at the source end of the gate. For a long gate length HEMT, Eq. (8.9) is valid until the onset of donor charge modulation, that is, 0 <ns<nsm. The intrinsic transconductance of thedevice obtained by differentiating this expression with respect to the gate voltage and is expressed as follows: (8.10) For a short gate length HEMT, the electric field in the channel is much greater in magnitude than thecritical electric field Ec. Assuming that the entire channel of the FET operates in saturated velocity mode, we can make the following assumption, that is, Vg–Vc(0) –Vth >> EcLg. Then using Eqs. (8.1), (8.9), and (8.10) are reduced to the following: (8.11) (8.12) More insight can be obtained in terms of device parameters if the equation for charge control [Eq. (8.1)] is substituted in the expressions for Ids and Vg as follows: (8.13) (8.14) where nc = EcCsLg /q and 0 < ns < nsm. Dividing both sides of Eq. (8.14) by Csvsat the following expression for modulation efficiency is obtained: (8.15) Hence it is necessary to maximize the 2DEG density ns to maximize the current drive, transconductance, and modulation efficiency of the HEMT. Although this is in contrast with the saturated-velocity model, it agrees with the experimental results. The foregoing results can also be used to select the appropriate material system and layer structure for the fabrication of high-performance microwave and millimeterwave HEMTs. Although the analytical model of device operation as was described here provides great insight into the principles of device operation and performance optimization, it fails to predict some of the nonlinear phenomena such as reduction of gm at high current levels (gm compression) and soft pinchoff characteristics. A model has been developed to explain these phenomena.5 The total charge in the HEMT is divided into three components. The first, QSVM, is the charge required to support a given Ids under the saturated velocity model (SVM). This charge is uniformly distributed under the gate. In reality this is not the case as the electron velocity under the gate varies. To maintain the current continuity under the gradual channel approximation (GCA), extra charge under the channel has to be introduced. This is defined as QGCA and is maximum at the source end of the gate and minimum at the drain end. The excess charge in the wide bandgap electron supply layer is denoted by QSL. Figure 8.2 shows the location and distribution of these charges in the HEMT. Only QSVM supports current density and thus contributes to the transconductance of the HEMT. The other two components contribute only to the total capacitance of the device. Hence the modulation efficiency (ME) of the HEMT in terms of these charges is expressed as (8.16) and the transconductance can be expressed as gm = Csvsat η. Figure 8.3 shows the variation of ME as a function of drain current density for an AlGaAs/GaAs HEMT and an AlGaAs/InGaAs pHEMT. At low current density, ME is low as most of the charge in the 2DEG channel has to satisfy the gradual channel approximation. This low value of ME results in low transconductance and soft pinch-off characteristics at low drain current densities. In the high current regime, modulation of QSL reduces the ME, resulting in gain compression. In the intermediate current regime the ME is maximum. However, if there exists a bias condition where both QGCA and QSL are modulated (as in the low band offset AlGaAs/GaAs system), it severely affects the ME. For optimal high-power and high-frequency performance, it is necessary to maximize the range of current densities in which ME is high. The drop off in ME due to parasitic charge modulation in the donor layers can be pushed to higher current density by increasing the maximum 2DEG density nsm. The 2DEG density can be maximized by using planar doping in the donor layer and by increasing the conduction band discontinuity at the barrier/2DEG interface. The drop off in ME due to operation in gradual channel mode can be pushed to lower current densities by reducing the saturation voltage VDsat. This is achieved by increasing the mobility of the electrons in the 2DEG channel and by reducing the gate length. As seen from Fig. 8.3 higher modulation efficiency is achieved over a larger range of current density for the AlGaAs/InGaAs pHEMT, which has higher sheet charge density, mobility, and band discontinuity at the interface than the AlGaAs/GaAs HEMT. Small Signal Equivalent Circuit Model of HEMT The small signal equivalent circuit model of the HEMT is essential for designing HEMT-based amplifiers. The model can also provide insights into the role of various parameters in the high-frequency performance of the device. Figure 8.4 shows the small signal equivalent circuit for a HEMT. The grey box highlights the intrinsic device. The circuit elements in the preceding model are determined using microwave S-parameter measurements.7,8 The intrinsic circuit elements are a function of the DC bias, whereas the extrinsic circuit elements or parasitics are independent of it. The two measures of the high frequency performance of a FET can now be defined in terms of the small signal model of the device as follows. The current gain cutoff frequency, fT can be defined as (8.17) Hence, to increase the current gain cutoff frequency it is essential to increase the gm and reduce Cgs and Cgd. Referring to Eq. (8.18), it is clear that this can be achieved by increasing electron velocity in the channel and reducing gate length. The current gain cutoff frequency is mainly a physical measure of device performance. A more practical measure of high-frequency device performance is fmax, the power gain cutoff frequency. This is the frequency at which the power gain of the FET is unity. It is defined as follows, (8.18) A simple form of Eq. (8.18) is: (8.19) To improve the fmax of the device it is necessary to minimize the quantities in the denominator of Eq. (8.18). The crucial parameters here are the output conductance of the device gds, the source and gate parasitic resistances Rs and Rg, and the gate-drain feedback capacitance Cgd that need to be minimized. Reduction of gds can be achieved by appropriate vertical scaling (to be discussed in the next section). Reduction of Rs and Rg depends mainly on the process technology. Reduction of Cgd can be achieved by proper design of the gate-drain region of the FET. The crucial parameter in the design of the gate drain depletion region is the gate-drain separation Lgd.10 Increasing Lgd reduces Cgd but also increases the effective gate length of the device, reducing the short channel effects. The optimum value of Lgd is 2.3 times that of the gate length Lg. Thus it is clear that fmax is a better measure of the high-frequency performance of a FET as it is determined not only by the material system used but also by the process technology and device design parameters. Large signal models of HEMTs are essential for designing power amplifiers and are similar to those of MESFETs. Scaling Issues in Ultra-High-Speed HEMTs The frequency at which a HEMT operates is limited by the electron transit time from the source to the drain. Therefore to increase the frequency of operation it is necessary to reduce the gate length. However, as the gate length approaches 0.1 μm it is necessary to reduce the other parasitic delays in the device and take into account short channel effects to maintain the high-frequency performance of the HEMT. Delay Time Analysis The reduction of parasitic delays in a FET is essential to improve the high frequency performance as these delays can be as high as 45% of the intrinsic delay.11 Considering the small-signal model of a FET, the total delay tT in a FET can be expressed as follows: (8.20) Here tpad is the charging time for the parasitic pad capacitance and is given by (8.21) where Cpad is the pad capacitance and is typically 10 fF per 50 μm × 50 μm bonding pad, gm is the extrinsic transconductance per unit gate width, and W is the width of the device. To minimize tpad it is necessary to have a high gate width, high transconductance HEMT. The gate fringe capacitance charging time (tfringe) is given by (8.22) where gmo is the intrinsic transconductance of the HEMT and is related to the extrinsic transconductance (gm) and source resistance Rs by the following expression: (8.23) The gate fringe capacitance Cfringe is typically 0.18 pF/mm, hence for a HEMT with an intrinsic transconductance of 1000 to 1500 mS/mm, tfringe is approximately 0.1 to 0.2 ps. Channel charging delay tchannel is associated with RC delays and is proportional to channel resistance. The channel charging delay is minimum at high current densities. The channel charging delay can be considered as a measure of the effectiveness of a FET operating in the saturated velocity mode. The transit delay of the FET, ttransit, can be expressed as the time required to traverse under the gate and is given by (8.24) The drain delay (tdrain) is the time required by the electron to traverse the depletion region between the gate and the drain and is a function of bias conditions.13 The drain delay increases with drain bias as the length of the depletion region beyond the gate increases. Drain delay is an important parameter for millimeter-wave power HEMTs. To increase the breakdown voltage of the device, the gate-to-drain spacing has to be increased. When the device is biased at a high drain voltage to maximize the power output, it creates a drain depletion region that is on the order of gate length of the device. Thus the drain delay becomes a major component of the total delay in the device, and can limit the maximum fT and fmax. Vertical Scaling Aspect ratio (the ratio between the gate length Lg and the gate-to-channel separation dBarrier) needs to be maintained when gate length is reduced. Aspect ratio is a critical factor affecting the operation of the field effect transistor and should be maintained above five. As the gate length is reduced, the distance between the gate and 2DEG (the distance dn + di as seen in Fig. 8.1) has to be reduced so that the aspect ratio of the device is maintained. However, maintaining the aspect ratio alone does not guarantee improvement in device performance. This is clear if the variation of threshold voltage with the reduction in dBarrier is examined. It is clear that di cannot be reduced, as it will result in degradation of mobility in the 2DEG channel due to scattering from the donors in the barrier layers. Therefore, to maintain aspect ratio, the thickness of the doped barrier layer dn has to be reduced. By examining Eq. (8.3) for threshold voltage, it is clear that this makes the threshold voltage more positive. At first glance, this does not seem to affect device performance. The effect of the more positive threshold voltage is clear if the access regions of the device are considered. A more positive threshold voltage results in reduction of sheet charge in the access region of the device. This increases the source and drain resistance of the device, which reduces the extrinsic transconductance [see Eq. (8.23)] and also increases the channel charging time (due to increased RC delays). Thus the increased parasitic resistances nullify the improvements in speed in the intrinsic device. The threshold voltage of the device must be kept constant with the reduction in dn. From Eq. (8.3) it can be seen that the doping density in the high bandgap donor has to be increased. Since the threshold voltage varies as a square of the doped barrier thickness, a reduction in its thickness by a factor of 2 requires that the doping density be increased by a factor of 4. High doping densities can be difficult to achieve in wide bandgap materials such as AlGaAs due to the presence of DX centers. Increased doping also results in higher gate leakage current, higher output conductance, and a lower breakdown voltage. Utilizing planar or delta doping wherein all the dopants are located in a single plane can alleviate these problems. This leaves most of the higher bandgap layer undoped and enables reduction of its thickness. The threshold voltage of a planar-doped HEMT is given as follows (8.25) where N2D is the per unit area concentration of donors in the doping plane and dn is the distance of the doping plane from the gate. In this case, the 2D doping density has to increase linearly with the reduction in barrier thickness. The transfer efficiency of electrons from the donors to the 2DEG channel also is increased, as all the dopant atoms are close to the 2DEG channel. Hence higher 2DEG sheet densities can be achieved in the channel and thus planar doping enables efficient vertical scaling of devices with reduction in gate length.15 From a materials point of view, efficient vertical scaling of a HEMT requires a high bandgap donor/barrier semiconductor that can be doped efficiently. The voltage gain of the device (gm/gds) can be considered as a measure of short channel effects in the device. The reduction of gate length and the gate-to-channel separation results in an increase in the transconductance of the device. However, to reduce the output conductance gds of the device, it is also necessary to reduce the channel thickness, which then increases the carrier confinement in the channel. Enoki et al. have investigated the effect of the donor/barrier and channel layer thickness on the voltage gain of the device.16 The gate-to-channel separation (dBarrier) and the channel thickness (dchannel) were varied for a 0.08-μm gate length AlInAs/GaInAs HEMT. For a dBarrier of 170 Å and a dchannel of 300 Å, the gm was 790 mS/mm and gds was 99 mS/mm, resulting in a voltage gain of 8. When dBarrier was reduced to 100 Å and dchannel was reduced to 150 Å, the gm increased to 1100 mS/mm and gds reduced to 69 mS/mm; this doubled the voltage gain to 16. This illustrates the necessity to reduce the channel thickness to improve charge control in ultra-short gate length devices. Subthreshold slope is an important parameter to evaluate short channel effects for digital devices. A high value of subthreshold slope is necessary to minimize the off-state power dissipation and to increase the device speed. Two-dimensional simulations performed by Enoki et al. indicate that reduction in channel thickness is more effective than the reduction in barrier thickness, for maintaining the subthreshold slope with reduction in gate length.The high-frequency performance of a device is a function of the electrical gate length Lg,eff of the device, which larger than the metallurgical gate length Lg due to lateral depletion effects near the gate. The relation between Lg,eff and Lg is given by, (8.26) where dBarrier is the total thickness of the barrier layers, Δd is the distance of the centroid of the 2DEG from the channel barrier interface and is on the order of 80 Å. The value of parameter β is 2. Consider a long gate length HEMT (Lg = 1 μm) with a barrier thickness of 300 Å. Using Eq. (8.26), the value of 1.076 μm is obtained for Lg,eff. Thus the effective gate length is only 7.6% higher than the metallurgical gate length. Now consider an ultra-short gate length HEMT (Lg = 0.05 μm) with an optimally scaled barrier thickness of 100 Å. Using the same analysis, a value of 0.086 μm is obtained for Lg,eff. In this case the effective gate length is 43% higher than the metallurgical gate length. Hence, to improve the high-frequency performance of a ultra-short gate length HEMT, effective gate length reduction along with vertical scaling is required. Horizontal Scaling Reduced gate length is required for the best high-frequency performance. However, it should be kept in mind that the gate series resistance increases with the reduction in gate length. This problem can be solved with a T-shaped gate. This configuration lowers the gate series resistance while maintaining a small footprint. Another advantage of the T-shaped gate is reduced susceptibility to electromigration under large signal RF drive as the large gate cross-section reduces current density. For a 0.1-μm gate length using a T-gate instead of a straight gate, reduces the gate resistance from 2000 Ω/mm to 200 Ω/mm. The simplified expression for fT as expressed in Eq. (8.17) does not include the effect of parasitics on the delay time in a FET. A more rigorous expression for fT, which includes the effects of parasitics on fT was derived by Tasker and Hughes and is given here, (8.27) It is clear from Eq. (8.27) that it is necessary to reduce source and drain resistances Rs and Rd, respectively, to increase the fT of a FET. Mishra et al. demonstrated a record fT of 250 GHz for a 0.15-μm device with a self-aligned gate, which reduces the gate-source and gate-drain spacing and results in the reduction of Rs and Rd.18 Equation (8.27) can be rearranged as follows, (8.28) where the first term on the right-hand side is the intrinsic delay of the device (τint) and the rest of the terms contribute to parasitic delay (τp). From this equation the ratio of parasitic delay to the total delay (τt = τp + τint) is given as (8.29) Hence to improve the fT of the device, the parasitic source and drain resistance have to be reduced as the gate length of the device is reduced. This minimizes the contribution of the parasitic delays to the total delay of the device. Material Systems for HEMT Devices The previous portions of this section discussed the various device parameters crucial to high-frequency performance of HEMTs. In this section the relationship between material and device parameters will be discussed. This will enable the selection of the appropriate material system for a particular device application. Table 8.1 illustrates the relationship between the device parameters and material parameters for the various constituent layers of the HEMT, namely the high bandgap donor and buffer layers, and the 2DEG channel. Figure 8.5 shows a schematic diagram of a HEMT, illustrating the material requirements from each component layer. The first HEMT was implemented in the lattice-matched AlGaAs/GaAs system in 1981. The AlGaAs/ GaAs HEMT demonstrated significant improvement in low noise and power performance over GaAs MESFET due to superior electronic transport properties of the 2DEG at the AlGaAs/GaAs interface and better scaling properties. However, the limited band discontinuity at the AlGaAs/GaAs interface limits the 2DEG sheet charge density. Other undesirable effects, such as formation of a parasitic MESFET in the donor layer and real space transfer of electrons from the channel to donor, are prevalent, however. One way to increase band discontinuity is to increase the Al composition in AlGaAs. However, the presence of deep level centers (DX centers) associated with Si donors in AlGaAs prevents the use of high Al composition AlGaAs donor layers to increase the band discontinuity and also limits doping efficiency. Problems relating to low band discontinuity can also be solved by reducing the bandgap of the channel, and by using a material that has higher electron mobility and electron saturation velocity. The first step in this direction was taken by the implementation of an AlGaAs/InGaAs pseudomorphic HEMT (GaAs pHEMT).20 In an AlGaAs/InGaAs pHEMT the electron channel consists of a thin layer of narrow bandgap InGaAs that is lattice mismatched to GaAs by 1 to 2%. The thickness of the InGaAs channel is thin enough (~200 Å) so that the mismatch strain is accommodated coherently in the quantum well, resulting in a dislocation free "pseudomorphic" material. However the indium content in the InGaAs channel can be increased only up to 25%. Beyond this limit the introduction of dislocations due to high lattice mismatch degrades the electronic properties of the channel. The maximum Al composition that can be used in the barrier is 25% and the maximum indium composition that can be used in the channel is 25%. Using the Al0.48In0.52As/Ga0.47In0.53As material system lattice matched to InP can simultaneously solve the limitations of the high bandgap barrier material and the lower bandgap channel material. The AlInAs/ GaInAs HEMT (InP HEMT) has demonstrated excellent low-noise and power performance that extends well into the millimeter-wave range; they currently hold all the high-frequency performance records for FETs. The GaInAs channel has high electron mobility (>10,000 cm2/Vs at room temperature), high electron saturation velocity (2.6 × 107 cm/s) and higher intervalley (Γ-L) energy separation. The higher conduction band offset at the AlInAs/GaInAs interface (ΔΕc = 0.5 eV) and the higher doping efficiency of AlInAs (compared to AlGaAs) results in a sheet charge density that is twice that of the AlGaAs/InGaAs material system. Higher doping efficiency of AlInAs also enables efficient vertical scaling of short gate length HEMTs. The combination of high sheet charge and electron mobility in the channel results in low source resistance, which is necessary to achieve high transconductance. However, the low bandgap of the InGaAs channel results in low breakdown voltage due to high impact ionization rates. Table 8.2 summarizes the material properties of the three main material systems used for the fabrication of HEMTs. The emergence of growth techniques like Metal Organic Chemical Vapor Deposition (MOCVD) and Gas Source Molecular Beam Epitaxy (GSMBE) and continuing improvement in the existing growth techniques like molecular beam epitaxy (MBE) have enabled a new class of phosphorusbased material systems for fabrication of HEMTs. On the GaAs substrate, the GaInP/InGaAs has emerged as an alternative to the AlGaAs/InGaAs material system. GaInP has a higher bandgap than AlGaAs and hence enables high 2DEG densities due to the increased conduction band discontinuity (ΔEc) at the GaInP/InGaAs interface. As GaInP has no aluminum it is less susceptible to environmental oxidation. The availability of high selectivity etchants for GaAs and GaInP simplifies device processing. However, the high conduction band discontinuity is achieved only for disordered GaInP, which has a bandgap of 1.9 eV. Using graded GaInP barrier layers and an In0.22Ga0.78As channel, 2DEG density as high as 5×10^12/cm^2 and a mobility of 6000 cm^2/Vs was demonstrated. On InP substrates, the InP/InGaAs material system can be used in place of the AlInAs/GaInAs material system. The presence of deep levels and traps in AlInAs degrades the low frequency noise performance of AlInAs/GaInAs HEMT. Replacing the AlInAs barrier by InP or pseudomorphic InGaP can solve this problem. One disadvantage of using the InP-based barrier is the reduced band discontinuity (0.25 eV compared to 0.5 eV for AlInAs/GaInAs) at the InP/InGaAs interface. This reduces 2DEG density at the interface and modulation efficiency. Increasing the indium content up to 75% in the InGaAs channel can increase the band discontinuity at the InP/InGaAs interface. The poor Schottky characteristics on InP necessitate the use of higher bandgap InGaP barrier layers or depleted p-type InP layers. A sheet density of 3.5 × 1012/cm2 and mobility of 11,400 cm2/Vs was demonstrated in an InP/In0.75Ga0.25As/InP double heterostructure. Despite the large number of material systems available for fabrication of HEMTs, the GaAs pHEMT implemented in the AlxGa1-xAs/InyGa1-yAs (x ~ 0.25; y ~ 0.22) material system and the InP HEMT implemented in the Al0.48In0.52As/Ga0.47In0.53As material system have emerged as industry vehicles for implementation of millimeter-wave analog and ultra high-speed digital circuits. The next two portions of this section will discuss the various performance aspects of GaAs pHEMT and InP HEMT. AlGaAs/InGaAs/GaAs Pseudomorphic HEMT (GaAs pHEMT) The first AlGaAs/InGaAs pseudomorphic HEMT was demonstrated in 1985. Significant performance improvement over AlGaAs/GaAs HEMT was observed. Devices with a 1-μm gate length had peak transconductance of 270 mS/mm and maximum drain current density of 290 mA/mm.20 The current gain cutoff frequency (fT) was 24.5 GHz and the power gain cutoff frequency (fmax) was 40 GHz. An fT of 120 GHz was reported for 0.2-μm gate length devices with In0.25Ga0.75As channel.24 Devices with a 0.1-μm gate length with an fmax of 270 GHz were demonstrated in 1989. Millimeter-Wave Power GaAs pHEMT In the past few years, the GaAs pHEMT has emerged as a device of choice for implementing microwave and millimeter-wave power amplifiers. To achieve a high output power density, device structures with higher current density and consequently higher sheet charge are required. As the sheet charge density in a single heterojunction AlGaAs/InGaAs pHEMT is limited to 2.3 × 10^12/cm2, a double heterojunction (DH) device structure must be used to increase the sheet charge. In a DH GaAs pHEMT, carriers are introduced in the InGaAs channel by doping the AlGaAs barriers on both sides of the InGaAs channel. The AlGaAs barriers are doped with silicon using atomic planar doping to increase the electron transfer efficiency. A typical charge density of 3.5 × 10^12/cm^2 and a mobility of 5000 cm^2/Vs is obtained for a double heterojunction GaAs pHEMT structure. The high sheet charge thus obtained enables higher current drive and power handling capability. Figure 8.6 shows the layer structure of a typical millimeterwave power GaAs pHEMT. In some cases a doped InGaAs channel is also used to increase sheet charge density. Breakdown voltage is an important parameter for power devices. A device with high breakdown voltage can be biased at high drain voltages, which increases the drain efficiency, voltage gain, and power added efficiency (PAE). Typical breakdown voltages of GaAs pHEMTs range from 8 to 15 V. The breakdown mechanism of a GaAs pHEMT can be either at the surface in the gate-drain of the device or in the channel (due to impact ionization). There are several approaches used to increase the breakdown voltage of a GaAs pHEMT. The planar doping of AlGaAs barriers (as already described) helps in maintaining a high breakdown voltage, as most of the AlGaAs barrier is undoped. Another approach to increase the breakdown voltage uses a lowtemperature grown (LTG) GaAs buffer below the channel. Using this approach, a 45% increase in channel breakdown voltage with a 12% increase in output power was demonstrated.27 Using a double recessed gate structure to tailor the electric field in the gate drain depletion region can also increase breakdown voltage. The increase in breakdown voltage is mainly due to reduction in the electric field at the gate edge by surface states in the exposed recess region. The output power obtained from a HEMT also depends on the biasing conditions. To achieve high efficiency devices (as in Class B operation), the device is biased near pinch off, and therefore, high gain is required near pinch off. The mode of operation is ideally suited for pHEMTs, which typically have high transconductance near pinch off due to their superior charge-control properties. The effect for gate bias on the power performance of HEMT has been investigated.29 Higher gain is achieved under Class A conditions. Biasing the device at higher drain voltages can increase the output power. Table 8.3 presents a summary of power performance of GaAs pHEMTs at various microwave and millimeter-wave frequencies. From Table 8.3 it can be seen that at a given frequency, the device power output and gain increases with a decrease in gate length due to better high-frequency operation. Reduction in power gain is also observed for wider devices. This is due to the increase in source inductance, which increases with gate width and frequency and is due to the increase in gate resistance as a square of gate width. Low inductance via hole source grounding and proper gate layout is required to reduce these parasitics. Reliability is important for space applications, typically a mean-time-to-failure (MTTF) of 107 h (1142 yr) is required for space applications. GaAs pHEMTs have demonstrated a MTTF of 1 × 107 h at a channel temperature of 125°C. The main failure mechanism is the atmospheric oxidation of the exposed AlGaAs barrier layers and interdiffusion of the gate metallization with the AlGaAs barrier layers (gate sinking). Using dielectric passivation layers to reduce the oxidation of AlGaAs can solve these problems. Using refractory metal for gate contacts will minimize their interaction with the AlGaAs barrier layers. A MTTF of 1.5 × 107 hours at a channel temperature of 150°C was achieved using Molybdenum based gate contacts. Traveling wave tubes (TWT) have been traditionally used as multiwatt power sources for microwave applications up to K-band (20 GHz). Using GaAs pHEMT in place of TWT for these applications has many advantages, including lower cost, smaller size, smaller weight, and higher reliability. However, the typical power density of a GaAs pHEMT at 20 GHz is on the order of 1 W/mm. Hence, the output power from a large number of devices has to be combined. To minimize combining losses, it is desirable to maximize power output of a single device. When large devices (gate width on the order of mm) are used to increase the total power output, other factors such as device layout, input signal distribution, output power combining networks, and substrate thickness are of critical importance. Several multiwatt GaAs pHEMT power modules have been demonstrated recently. A power module with 9.72-mm wide GaAs pHEMTs that delivered an output power of 4.7 W in the 18 to 21.2 GHz band with a PAE of 38% was demonstrated.45 Table 8.4 summarizes the recent results of multiwatt GaAs pHEMT power modules Low Noise GaAs pHEMTs Figure 8.7 shows the structure of a generic low-noise GaAs pHEMT. As the drain current requirement for a low-noise bias is low, single-side doped heterojunctions are sufficient for low-noise devices. The emphasis here is on achieving higher mobility to reduce the parasitic source resistance. As already discussed, the AlInAs/GaInAs material system is the ideal choice for fabrication of low-noise microwave and millimeter-wave devices. However, GaAs pHEMTs also find significant use in millimeter-wave low noise applications due to wafer size, cost, and process maturity related advantages. Henderson et al. first reported on the low noise performance of GaAs pHEMTs in 1986. Devices with 0.25-μm gate length had a noise figure of 2.4 dB and an associated gain of 4.4 dB at 62 GHz.51 A 0.15-μm gate length Al0.25Ga0.75As/In0.28Ga0.72As pHEMT with a noise figure of 1.5 dB and an associated gain of 6.1 dB at 61.5 GHz was demonstrated in 1991.52 The reduction in noise figure was a direct result of reducing the gate length, which increased the fT of the device. Low noise operation of a GaAs pHEMT was also demonstrated at 94 GHz.53 For a 0.1-μm gate length device a noise figure of 3.0 dB and associated gain of 5.1 dB was achieved. A noise figure of 2.1 dB and an associated gain of 6.3 dB was reported for a 0.1 μm gate length GaAs pHEMT at 94 GHz.54 The improvement in noise figure is attributed to the use of a T-shaped gate with end-to-end resistance of 160 Ω/mm by Tan et al.,52 compared to a trapezoidal gate with end-to-end resistance of 1700 Ω/mm used by Chao et al.53 This further emphasizes the need to reduce parasitic resistances in low-noise devices. One of the main system applications of low-noise GaAs pHEMTs is satellite direct broadcasting receiver systems (DBS) that are in increasing demand worldwide. Low-noise amplifiers operating at 12 GHz are a critical component in these systems. The low-noise performance of GaAs pHEMTs is more than adequate for these applications. A 0.25-μm gate length GaAs pHEMT with a noise figure of 0.6 dB and an associated gain of 11.3 dB at 12 GHz was reported by Tokue et al.55 Performance coupled with low cost packaging is one of the crucial factors in the high volume DBS market. Hwang et al. have demonstrated a 0.2-μm gate length GaAs pHEMT in plastic packaging with a 1.0 dB noise figure and 9.9 dB associated gain at 12 GHz.56 A plastic packaged GaAs pHEMT device with a gate length of 0.17 μm demonstrated a noise figure of 0.35 dB, and 12.5 dB associated gain at 12 GHz.57 Table 8.5 summarizes the low-noise performance of GaAs pHEMTs at various microwave and millimeter-wave frequencies. GaAs pHEMT for Wireless Applications The explosive growth of the wireless communication industry has opened up a new area of application for GaAs pHEMTs. Unlike the millimeter-wave military and space applications, the frequencies of operation of these applications are much lower. The frequencies used in typical cellular phones range from 850 MHz for the American Mobile Phone System (AMPS) to 1.9 GHz for the Japanese Personal Handy Phone System (PHS) and the Digital European Cordless Telephone (DECT). The device parameters of interest when considering device technologies for wireless applications are operating voltages, which must be positive, power density, output match and linearity requirements, and gate leakage current. Using enhancement mode devices (threshold/pinch-off voltage > 0) eliminates the negative supply voltage generator and power-cutoff switch. The high gate turn-on voltage of an enhancement mode GaAs pHEMT, as compared to the enhancement mode GaAs MESFET, enables higher input voltage swing. The power performance of MESFET and GaAs pHEMT for wireless applications has been compared. For the same saturation drain current density, at a frequency of 950 MHz, the saturated power output from the pHEMT is 2.5 W, whereas it is 1.8 W from the MESFET. The power-added efficiency of the pHEMT is 68%, which is 8% higher than that of the MESFET. This difference is due to the transfer characteristics of the two devices. The pHEMT performs as a better power amplifier than the MESFET because the input power is effectively amplified with higher gm near the pinch-off voltage. This is a direct consequence of better charge control properties of the HEMT when compared to the MESFET. The pHEMT also has a lower gate leakage current than the MESFET due to a higher Schottky barrier on AlGaAs. The power performance of enhancement mode GaAs pHEMT with a threshold voltage of 0.05 V for wireless applications has also been investigated.60 A device with a gate width of 3.2 mm delivered an output power of 22 dBm with power-added-efficiency of 41.7%. The standby current at a gate bias of 0 V was 150 μA. Enhancement mode GaAs HFET with a higher threshold voltage of 0.5 V has also been demonstrated. A 1-μm gate length device with a gate width of 12 mm delivered an output power of 31.5 dBm with a PAE of 75% at 850 MHz and at a drain bias of 3.5 V. The standby current at a gate bias of 0 V was 1 μA. This eliminates the need for a switch in the drain current of the power amplifier. The device was manufactured using Motorola's CGaAs process, which is cost effective as it uses processes that are similar to standard silicon MOS and bipolar processes. Table 8.6 shows a summary of power performance of GaAs pHEMTs for cellular phones. AlInAs/GaInAs/InP (InP HEMT) Future military and commercial electronic applications will require high-performance microwave and millimeter-wave devices. Important applications include low-noise amplifiers for receiver front ends, power amplifiers for phased-array radars, ultra high-speed digital circuits for prescalers, and MUX/DEMUX electronics for high-speed (> 40 Gb/s) optical links. A HEMT device capable of operating at millimeter-wave frequency requires a channel with high electron velocity, high current density, and minimal parasitics. As discussed, the Al0.48In0.52As/Ga0.47In0.53As material system lattice matched to InP satisfies these criteria. A 1-μm gate length AlInAs/GaInAs HEMT with extrinsic transconductance as high as 400 mS/mm was demonstrated.77 The microwave performance of 1-μm gate-length devices showed an improvement of 20 to 30% over the AlGaAs/GaAs HEMT.78 In 1988 Mishra et al. demonstrated a 0.1 μm InP HEMT with a fT of 170 GHz.79 Using a T-gate to self-align the source and drain contacts results in reduction of source-gate and source-drain spacing. This not only reduces the parasitic source and drain resistances, but also the drain delay. Using the preceding technique an fT of 250 GHz was achieved in a 0.13-μm gate length self-aligned HEMT.18 Recently, a 0.07-μm AlInAs/ GaInAs HEMT with an fT of 300 GHz and an fmax of 400 GHz was reported.80 The high-frequency performance of the InP HEMT can be further improved by using a pseudomorphic InGaAs channel with an indium content as high as 80%. The fT of a 0.1-μm InP HEMT increased from 175 to 205 GHz when the indium content in the channel was increased from 53 to 62%.81 Although devices with high indium content channels have low breakdown voltages, they are ideal for low noise applications and ultra high-speed digital applications. An fT of 340 GHz was achieved in a 0.05-μm gate length psuedomorphic InP HEMT with a composite In0.8Ga0.2As/In0.53Ga0.47As channel.82 This is the highest reported fT of any 3-terminal device. Compared to the GaAs pHEMT, the AlInAs/GaInAs HEMT has a higher current density that makes it suitable for ultra high-speed digital applications. The high current gain cutoff frequency and low parasitics make the AlInAs/GaInAs HEMT the most suitable choice for low- noise applications extending well beyond 100 GHz. The high current density and superior high-frequency performance can be utilized for high-performance millimeter-wave power applications provided the breakdown voltage is improved. Some of the state-of-the-art millimeter-wave analog circuits and ultra high-speed digital circuits have been implemented using InP HEMTs. A low-noise amplifier with 12 dB gain at a frequency of 155 GHz using a 0.1-μm InP HEMT with a In0.65Ga0.35As psuedomorphic channel was demonstrated.83 Pobanz et al. demonstrated an amplifier with 5 dB gain at 184 GHz using a 0.1 μm gate In0.8Ga0.2As/InP composite channel HEMT. Low-Noise AlInAs/GaInAs HEMT The superior electronic properties of the GaInAs channel enable the fabrication of extremely high fT and fmax devices. The superior carrier confinement at the AlInAs/GaInAs interface results in a highly linear transfer characteristic. High transconductance is also maintained very close to pinch off. This is essential because the noise contribution of the FET is minimized at low drain current levels. Hence high gain can be achieved at millimeter-wave frequencies under low-noise bias conditions. The high mobility at the AlInAs/GaInAs interface also results in reduced parasitic source resistance of the device. AlInAs/GaInAs HEMTs with 0.25-μm gate length exhibited a noise figure of 1.2 dB at 58 GHz.85 At 95 GHz a noise figure of 1.4 dB with associated gain of 6.6 dB was achieved in a 0.15-μm gate length device. Table 8.7 summarizes the low-noise performance of AlInAs/GaInAs HEMTs. Millimeter-Wave AlInAs/GaInAs Power HEMT The millimeter-wave power capability of single heterojunction AlInAs/GaInAs HEMTs has been demonstrated. The requirements for power HEMT are high gain, high current density, high breakdown voltage, low access resistance, and low knee voltage to increase power output and power-added efficiency. The AlInAs/GaInAs HEMT satisfies all of these requirements with the exception of breakdown voltage. This limitation can be overcome by operating at a lower drain bias. In fact, the high gain and PAE characteristics of InP HEMTs at low drain bias voltages make them ideal candidates for battery-powered applications. Another advantage is the use of InP substrate that has a 40% higher thermal conductivity than GaAs. This allows higher dissipated power per unit area of the device or lower operating temperature for the same power dissipation. As low breakdown voltage is a major factor that limits the power performance of InP HEMTs, this section will discuss in detail the various approaches used to increase breakdown voltage. Breakdown in InP HEMT is a combination of electron injection from the gate contact and impact ionization in the channel. The breakdown mechanism in the off-state (when the device is pinched off) is electron injection from the gate. The low Schottky barrier height of AlInAs results in increased electron injection from the gate and, consequently, higher gate leakage current compared to the GaAs pHEMT. These injected hot electrons cause impact ionization in the high-field drain end of the GaInAs channel. The high impact ionization rate in the low bandgap GaInAs channel is the main mechanism that determines the on-state breakdown. Some of the holes generated by impact ionization are collected by the negatively biased gate and result in increased gate leakage. The potential at the source end of the channel is modulated by holes collected by the source. This results in increased output conductance. Lowering the electric field in the gate-drain region can reduce the impact ionization rate. This is achieved by using a double recess gate fabrication process that increases the breakdown voltage from 9 to 16 V. A gate-drain breakdown voltage of 11.2 V was demonstrated for 0.15-μm gate length devices with a 0.6-μm recess width.96 In addition, reduction in output conductance (gds) and gate-drain feedback capacitance (Cgd) was observed when compared to single recessed devices. The fmax of a double recessed device increased from 200 to 300 GHz.97 Hence, it is desirable for power devices. Another approach to reduce electric field in the gate-drain region is to use an undoped GaInAs cap instead of a doped GaInAs cap. The output conductance can be reduced from 50 to 20 mS/mm for a 0.15-μm gate length device by replacing the doped GaInAs cap by an undoped cap.99 This also improved the breakdown voltage from 5 to 10 V. The reduction in Cgd and gds resulted in an fmax as high as 455 GHz. Redistribution of the dopants in the AlInAs barrier layers can also increase breakdown voltage. An increase in breakdown voltage from 4 to 9 V is achieved by reducing doping in the top AlInAs barrier layer and transferring it to the AlInAs barrier layers below the channel. The gate leakage current can be reduced and the breakdown voltage increased by using a higher bandgap strained AlInAs barrier.100,101 By increasing the Al composition in the barrier layers from 48 to 70%, the gate-to-drain breakdown voltage was increased from 4 to 7 V. This also results in reduction of gate leakage as the Schottky barrier height increases from 0.5 to 0.8 eV. The use of Al0.25In0.75P as an Schottky barrier improves the breakdown voltage from –6 to –12V. The on-state breakdown can be improved in two ways. The first is to reduce the gate leakage current by the impact ionization generated holes by increasing the barrier height for holes. This was achieved by increasing the valence band discontinuity at the channel-barrier interface. The use of a strained 25-Å In0.5Ga0.5P spacer instead of AlInAs increases the valence band discontinuity at the interface from 0.2 to 0.37 eV. An on-state breakdown voltage of 8 V at a drain current density of 400 mA/mm for a 0.7-μm gate length InP HEMT was achieved by using a strained InGaP barrier. The various approaches to increase the breakdown voltage, as already discussed here, concentrate on reducing the electron injection from the Schottky gate and reducing the gate leakage current. These approaches also have an inherent disadvantage as Al-rich barriers result in high source resistance and are more susceptible to atmospheric oxidation. Additionally, these approaches do not address the problem of a high impact ionization rate in the GaInAs channel and carrier injection from contacts. In the recent past, various new approaches have been investigated to increase breakdown voltage without compromising the source resistance or atmospheric stability of the device. These include the junction-modulated AlInAs/GaInAs HEMT (JHEMT), the composite GaInAs/InP channel HEMT, and the use of regrown contacts. Table 8.8 summarizes the power performance of AlInAs/GaInAs HEMTs. GaInAs/InP Composite Channel HEMT The high speed and power performance of InP HEMT can be improved by the use of composite channels that are composed of two materials with complementing electronic properties. The high-speed performance of an InP HEMT can be improved by inserting InAs layers in the InGaAs channel. The current gain cutoff frequency of a 0.15-μm gate length device increased from 179 to 209 GHz due to improved electron properties. An fT as high as 264 GHz was achieved for a 0.08-μm gate length device. The GaInAs channel has excellent electronic properties at a low electric field, but suffers from high impact ionization at high electric fields. On the other hand, InP has excellent electronic transport properties at high fields but has lower electron mobility. In a composite InGaAs/InP channel HEMT, the electrons are in the InGaAs channel at the low field source end of the channel and are in the InP channel at the high field drain end of the channel. This improves the device characteristics at high drain bias while still maintaining the advantages of the GaInAs channel at low bias voltages. A typical submicron gatelength AlInAs/GaInAs HEMT has an off-state breakdown voltage (BVdsoff) of 7 V, and on-state breakdown voltage (BVdson) of 3.5 V. Using a composite channels, (30 Å GaInAs/50 Å InP/100 Å n+ InP), Matloubian et al. demonstrated a BVdsoff of 10 V and BVdson of 8 V for a 0.15-μm gate length device. A 0.25-μm GaInAs/InP composite channel HEMT with a two-terminal gate drain voltage of 18 V was also demonstrated. The increased breakdown voltage of a composite channel HEMT enables operation at a higher drain bias. This increases the drain efficiency and the PAE of the device. An output power of 0.9 W/mm with a PAE of 76% at 7 GHz was demonstrated for a 0.15-μm GaInAs/InP composite channel HEMT at a drain bias of 5 V.115 At 20 GHz, an output power density of 0.62 W/mm (280 mW) and a PAE 46% was achieved for a 0.15 μm gate length device at a drain bias of 6 V.113 At 60 GHz, a 0.15-μm GaInAs/InP composite channel HEMT demonstrated an output power of 0.35 W/mm, and a power gain of 6.2 dB with a PAE of 12% at a drain bias of 2.5 V Wide bandgap materials such as silicon carbide (SiC) and gallium nitride (GaN) are known as such because their bandgaps are much larger than those of more conventional semiconductors such as silicon, germanium, or gallium arsenide. 4H-SiC, for example, has a bandgap of 3.2 eV, and GaN has a bandgap of 3.4 eV, as compared to 1.11 eV for silicon. These materials have been studied in theory for over 30 years; however, it has only been in the past decade that device development from wide bandgap semiconductors has occurred at any level, with significant breakthroughs occurring in SiC substrate and epi technology in the late 1980s, and in GaN epi technology in the mid-1990s. The first commercial applications for wide bandgap materials were blue LEDs fabricated from SiC, later followed by blue LEDs with greatly increased brightness, from GaN-related materials. While these applications are not RF applications, they have helped drive development of these very new, experimental materials. In recent years, wide bandgap semiconductors have received a great deal of attention as a nearly ideal material for the fabrication of high speed, high power transistors [1–5], particularly for cellular base station, broadcast, and high frequency radar applications. The large bandgaps should allow SiC- and GaN-based transistors to have stable DC and RF operation at very high temperatures [6]. Several other material properties of wide bandgap materials also make them attractive for fabrication of high voltage, high power, and high frequency transistors. These include a high electric breakdown field of 3 to 4×10^6 V/cm, high saturated electron drift velocities of 1.5 to 2.2×10^7 cm/sec, and high thermal conductivity (for SiC substrates) of 4.9 W/cm-K. This article will present a basic description of figures of merit for microwave devices fabricated from wide bandgap materials, a very basic description of the operation of some of the commonly studied wide bandgap RF power transistors, a discussion of the material properties needed for RF power generation and how those properties translate into improved performance of microwave systems, and a summary of state-of-the-art wide bandgap high frequency device performance. The article will focus primarily on AlGaN/GaN HEMTs, SiC MESFETs, and SiC SITs, since they are currently the most mature and most widely studied wide bandgap RF device technologies. Figures of Merit for RF Power Transistors Virtually all RF systems require active circuit elements for use as oscillators, amplifiers, etc. These elements permit conversion of energy from DC bias sources to RF bands where the energy can be used to provide useful gain at specified frequencies. The ideal RF power transistor has high current, high breakdown voltage, and a low "knee" voltage (the voltage at which the transistor current saturates), as illustrated in Fig. 9.1. The device is given DC bias at one-half its maximum operating voltage and one-half or less of its maximum operating current, and any RF signal superimposed over the device is amplified over the I-V curve as shown in Fig. 9.1. The maximum possible RF output power of a transistor is [7] (9.1) where P out is the RF output power, VDS is the drain bias, VKnee is the knee voltage, and RL is the load resistance, which is determined by the bias current and voltage in the device. The Power Added Efficency (PAE), η, of the device is another important figure of merit, and quantifies the amount of DC bias that is converted to RF power: (9.2) The maximum efficiency for an RF transistor is 50% under class A operation (transistor is biased at 50% of its open channel current), or 78.5% under class B operation (transistor is biased at pinch off or Idq=0A); however, the maximum possible output power for the device remains unchanged with bias as long as the device is operated at 50% or less of its open channel current. Qualitatively, any RF drive in the region below the knee voltage will result only in resistive loss, which leads to lower output power, decreased gain, and lower efficiency. The increased resistive loss also leads to device heating that will further degrade device performance. Thus, the ideal RF transistor would have a knee voltage of 0V. Two other important figures of merit for a microwave transistor are gain and intermodulation distortion (IMD). Gain is generally quantified under both large-signal and small-signal conditions, and is the ratio of output power to input power for a device [8]. Intermodulation distortion, in its simplest sense, is a measure of how constant gain is in a device over a wide range of instantaneous drive conditions as induced by a large RF signal. Any variation of gain from its linear, or constant value will cause generation of new signals at harmonic frequencies. These harmonics can cause system level problems. For example, a harmonic signal could be in a channel that is adjacent to its carrier, and be mistaken for a signal in that adjacent channel. IMD becomes increasingly more important, particularly in cellular systems, as more and more carriers are used in a given bandwith with increasing technology capabilities. The unity current gain cutoff frequency of a device, ft, and the maximum frequency of oscillation, fmax, are both very important parameters. These two figures of merit will determine the highest frequency at which a device is useful as an amplifier. Finally, the power density of an RF transistor is very important for several reasons. Power density is most often expressed in units of watts/mm of gate periphery or watts/square cm of die area. For a given power rating, a high power density results in a smaller device, which will mean higher output impedance, easier matching, and possibly more power per die and/or fewer combining networks. Common RF Power Devices from Wide Bandgap Materials The three most commonly studied wide bandgap RF power devices are the SiC MESFET (Metal-Semiconductor Field Effect Transistor), the SiC SIT (Static Induction Transistor), and the AlGaN/GaN HEMT (High Electron Mobility Transistor), sometimes called an AlGaN/GaN MODFET (Modulation Doped Field Effect Transistor). A brief description of operation of these three devices follows. SiC MESFETs The MESFET was first proposed by Mead in 1966 [9], and fabricated in GaAs by Hooper and Lehrer in 1967 [10]. A basic schematic of a MESFET is shown in Fig. 9.2.a [11]. The MESFET is a planar device fabricated by growth of a thin, doped epitaxial layer located on either a semi-insulating substrate or a low-doped layer of conductivity type opposite to that of the channel material. MESFETs in SiC can be fabricated on substrates of the same conductivity as the device channel (typically, n-type), but with a 1 to 5 micron buffer layer of opposite conductivity between the channel and the substrate. High resistivity substrates are most desirable for high frequency devices and result in improved DC and RF performance for the transistor by better confining electrons to the conducting channel and reducing microwave losses. This will be described in more detail in the next section. In the MESFET, current is passed through the conducting channel by means of two ohmic contacts (the source and drain), which are typically separated by a distance of 3 to 10 μm. The actual dimensions are dependent upon the operating frequency, and smaller dimensions are used as operating frequency is increased. A rectifying Schottky contact (the gate) is located between the two ohmic contacts, and is typically 0.1 to 2 μm in length for modern microwave devices. Fig. 9.2b shows the DC I-V curves for a MESFET [11]. During operation, the drain contact is biased at a specified potential (positive drain potential for an n-channel device) and the source is grounded. The flow of current through the conducting channel is controlled by a combination of a negative DC (for n-channel devices) gate bias with a superimposed RF signal also at the gate. The DC bias sets the quiescent operating current for the device, while the RF signal modulates the channel current, thereby providing RF gain. The operation of the transistor is determined by the ability of the gate signal to effectively modulate and control the current in the conducting channel. For this reason, any electrons that leak into the substrate or through the gate electrode will lead to performance degradation. The availability of both high resistivity, low leakage substrates and high quality, low leakage Schottky barrier gates in SiC makes high performance SiC MESFETs possible for high voltage RF power applications. SiC SITs Static Induction Transistors (SITs) are useful as high power RF sources and amplifiers at UHF and microwave frequencies. This device was originally proposed by Nishizawa [12] as a power amplifier for applications such as audio amplifiers. A cross-section of the transistor is shown in Fig. 9.3a. The device has a structure very similar to a vacuum triode with source and drain contacts separated by a certain distance. Electrons are emitted from the source, which is generally at ground potential, and are accelerated to the drain, which is biased at a positive potential, where they are collected. A grid structure is located in the space between the source and drain electrodes so the charge carriers can be externally modulated. The RF gain of the device is determined by the efficiency with which the modulation is accomplished. The grid structure is generally fabricated using pn or Schottky junctions. SIT devices are capable of high voltage gain, but limited current gain. However, since the device has good impedance characteristics, high power gain is available and the device can be effectively used at frequencies significantly in excess of the ft for the device. SITs have four possible modes of operation, as illustrated in the I-V curves shown in Fig. 9.3b. These modes are ohmic, thermionic emission, space-charge limited current flow (SCLC), and space-charge limited current flow under saturated velocity conditions (SCLC with Vsat). Static induction transistors perform best when designed so they operate under either of the space-charge-limited current flow conditions. This occurs when the conducting channel is lightly doped so that the region between the grid bars is completely depleted of free charge under typical bias conditions. Under these conditions a saddle point potential is created in the conducting channel between the grid bars, and modulation of this potential controls the flow of current from drain to source. In this mode of operation the current that can flow through the device is limited by the number of electrons that can be forced to flow between the grid bars and through the saddle point potential. Since this region is depleted of free charge carriers, the injected charge flowing in the channel generates a space-charge that reduces the electric field in front of the moving charge, and increases the electric field behind it. The net result is that current flow is selflimited by the space charge of the moving electrons. This limits the density of charge and RF currents that can flow through the device and establishes a limit to the current drive capability of the device. The use of SiC offers improved RF performance for SIT transistors since the current density that flows through the semiconductor is a function of both the injected charge density and the velocity at which the electrons move. Since the saturated velocity of electrons in SiC is very high (i.e., vs= 2.2×10^7cm/sec [13]), a high channel current is possible by designing the device so that the magnitude of the electric field is above that necessary to maintain electron velocity saturation. Also, the use of highly doped n+ source and drain contact regions permit low resistance contacts to be fabricated, thereby minimizing the degrading effects of low electron mobility. The net result is that higher channel current can be achieved, and this results in good RF performance. AlGaN/GaN HEMTs AlGaN/GaN HEMTs (High Electron Mobility Transistors) are somewhat similar in structure and operation to SiC MESFETs, with the notable difference that they are heterojunction devices. A cross-section of an AlGaN/GaN HEMT is shown in Fig. 9.4. In this device, all of the conduction is in a channel formed by a sheet of charge immediately under the AlGaN/GaN heterojunction, with the channel usually being about 50 to 250Å total thickness. Typical sheet charge densities in the AlGaN/GaN materials system are 1 to 1.5 ×10^13 cm^–2, which is 3 to 10 times that normally seen in GaAs-based HEMTs. The charge in thisdevice can either come from doping in the AlGaN layer, which spills over into the lower energy GaNlayer or can be induced by the piezoelectric field found in strained GaN-based materials grown on heteroexpitaxial substrates like sapphire or SiC [14]. The thick GaN layer and the buffer layer, most often AlN, provide isolation from the substrate and carrier confinement. These devices have been fabricated most frequently on sapphire substrates, but have also been extensively studied on SiC substrates [15–16], and have recently been fabricated on p-type silicon wafers [17]. To date, the best AlGaN/GaN HEMT performance has been from devices utilizing semi-insulating SiC substrates. Like in the MESFET, current flows in the AlGaN/GaN HEMT from source to drain, induced by a bias at the drain, and the gate modulates charge through the channel through the same combination of DC bias and RF signal. The high sheet charge density in these structures creates a very high current density to complement the high breakdown voltage already inherent in the GaN channel material. The high sheet charge will also allow very low on-resistance, which will improve the microwave performance of the devices, and the combination of high current density with high voltage operation makes the AlGaN/GaN HEMT the transistor with the highest power density of the wide bandgap devices. Other Wide Bandgap Devices There are several other wide bandgap power devices that are beginning to be studied. These include AlGaN/GaN HBTs (Heterojunction Bipolar Transistors), which should have excellent efficiency and breakdown characteristics [18], MOS-HFETs (Metal Oxide-Semiconductor Heterojunction Field Effect Transistors), which are expected to have improved linearity as compared to AlGaN/GaN HEMTs [19], JFETs (Junction Field Effect Transistors), which should have very good high temperature performance [20], and IMPATT diodes, which are expected to generate power at very high frequencies with much greater efficiency and lower access resistances than their GaAs and InP-based counterparts. All of these devices are in their technological infancy, and have yet to demonstrate the remarkable RF results of the more conventional wide bandgap devices. Nevertheless, the potential for these devices to become important in the future should not be overlooked. In the meantime, the rest of this article will focus only on results from SiC MESFETs, SiC SITs, and AlGaN/GaN HEMTs. Desirable Material Properties for RF Power Transistors There are a number of semiconductor material properties that affect the performance of a high speed, high power transistor [1–2]. These include the bandgap, critical (breakdown) electric field, and thermal conductivity. Electron and hole transport properties, the saturated electron velocity, and the electric field at which electron velocity saturates will also strongly influence the DC and RF characteristics of a high frequency power transistor. Several of these properties are summarized in Table 9.1, which compares the material properties of Si, GaAs, 4H-SiC, and GaN. In addition to the properties summarized in Table 9.1, the electrical conductivity of the substrate material can strongly affect RF losses in a transistor. Finally, the ability to make both low resistance ohmic contacts and good rectifying Schottky contacts are critical to transistor fabrication and performance. Figure 9.5 attempts to capture some of the many relationships between material properties and power device and system performance. The system level advantage is particularly important as a metric for evaluating devices from wide bandgap materials, as that is where their real importance and impact for a customer or consumer will be evident. Critical or Breakdown Field SiC and GaN have critical fields of 3.5 MV/cm, five times that of Si or GaAs. This critical, or breakdown field of a material is possibly the most important material parameter for design of a high power density device, as it determines the highest operating voltage of a transistor for a given device design and channel doping, and thus limits the RF power swing in the device. Analagously, for a given voltage requirement, a higher breakdown field will allow a device designer to use a higher doping level in the device than for a lower breakdown field material, and, with the higher doping, tighter device dimensions. Higher operating voltage, as shown in Eq. (9.1), results in both higher power and higher power density in the device. Higher doping and reduced dimensions in an FET will also enable a device with increased transconductance, lower parasitic resistances, increased power gain, higher ft and fmax, and improved efficiency due to the decreased access resistances. Furthermore, large output power levels can be achieved through either high current or high voltage operation, but a device that obtains its power from high voltage rather than high current will be much smaller due to the fact that voltage scaling in a device only involves design changes in a device channel on the order of 1 to 2 μm, whereas high current devices require complete scaling of the device periphery. This becomes even more important for a very high power device as increased current in the linear region of device operation introduces more resistive heating, and further degrades device performance. In addition, a smaller geometry, high voltage part will have output impedance levels that are much larger than for a larger geometry, high current device of the same output power level, making the high voltage FET easier to incorporate into a circuit design. At a system level, the higher power density of a wide bandgap transistor will lead to more power per die, and thus a smaller die count per system, and greater bandwidth due to improved output impedance characteristics. Higher efficiency will translate into lower total energy usage for the microwave system in question, and smaller die sizes will use smaller and therefore cheaper packages. Thermal Conductivity The thermal conductivity of a material determines the ease with which heat generated from unconverted DC power can be removed from the device. Any temperature rise from undissipated heat will further degrade device performance by causing a drop in the mobility and saturated electron velocity in the transistor, which in turn causes the device to become progressively less efficient and to generate more heat. Thermal conductivity can also influence whether or not special packaging and/or system cooling become necessary for successful device operation. The thermal conductivity of SiC of 4.9 W/cm-K is three times that of Si and ten times that of GaAs or sapphire and, as such, is a tremendous advantage for SiC-based devices. Since GaN-based devices are grown on both sapphire and SiC substrates at the present time, the limiting thermal conductivity for these devices depends on the choice of substrate. Wide Bandgap A large bandgap is considered desirable for high voltage power devices for two reasons. First, the bandgap determines the upper temperature limit of device operation. This is particularly important when transistor scaling and power density are examined, as higher temperature operation makes it possible to design a smaller, denser device that will withstand the heat it generates under bias. Second, wide bandgap materials have been shown to be more resistant to radiation, such as α particles, which are known to be very destructive in Si MOS devices. The large bandgaps of 3.4 eV for GaN and 3.2 eV for 4H-SiC give these materials a high temperature performance advantage over Si and GaAs. In the system limit, a device that can withstand higher channel and ambient temperatures may be suitable for a cheaper package and relaxed system cooling requirements. Saturated Electron Velocity The saturated electron velocity of a material is very important for sub-micron gate length devices, which typically operate at very high electric fields. In this regime, the frequency performance (in particular, ft) of a device is largely determined by electron velocity. SiC has a measured saturated electron velocity of 2.2×10^7 cm/second, twice that of Si or GaAs, and GaN has an electron velocity of 1.5×10^7 cm/second, still significantly higher than that of Si or GaAs. The electric field at which the electron velocity saturates is also important as it determines how quickly the charge carriers can be accelerated to their saturated values. The saturation fields for GaN and SiC are 1.5 to 2.5×10^4 V/cm, or 2 to 8 times higher than the 3 to 8×10^3 V/cm values for GaAs and Si. The high saturation fields combined with the low mobilities of wide bandgap semiconductors result in devices that will have higher knee voltages and therefore will have to be operated at considerably higher supply voltages before they operate in a saturated electron velocity regime. This will move their optimal performance to much higher voltage levels than for more conventional semiconductor technologies. Overall, the high electron velocities, at whatever voltage is necessary, will contribute to a very high speed device and, as a result, as very high system frequency. Electron and Hole Mobilities A primary disadvantage of fabricating transistors from wide bandgap semiconductors is the relatively low values for electron and hole mobilities in these materials. Electron and hole transport properties are also critical to successful device performance, and play a dominant role in determining the on-resistance and knee voltage of a device in its low-field region of operation. Low mobility results in increased parasitic resistance, increased losses, and reduced gain. These problems are worsened both as operating frequency is increased, where series resistances play an increasingly stronger role, and at elevated temperatures, where mobility will rapidly decrease. SiC and GaN have electron mobilities of 800 to 1000 cm^2/V-sec in nominally undoped material. These values are much less than the 1350 cm^2/V-sec electron mobility of silicon, let alone the 6000 cm^2/V-sec electron mobility of GaAs. At the typical 10^17cm^–3 doping levels commonly seen in high voltage MESFETs, the electron mobility in 4H-SiC drops to around μe ~ 500 cm^2/V-sec. Fortunately, the electron mobility in a 2D-gas in an AlGaN/GaN heteostructure typically remains close to 1000 cm^2/V-sec as the electrons in the AlGaN/GaN heterojunction are physically separated from their donor atoms and thus are not affected by ionized impurity scattering as in the case of SiC. The hole mobility in both SiC and GaN is very low, on the order of μp ~ 120 to 300 cm^2/V-sec. The low value for hole mobility severely limits the use of p-type SiC in RF transistors that are intended for operation above about 1 GHz. Substrate Conductivity In addition to the material properties detailed in Table 9.1, there are several other material parameters than can affect RF power device performance. The electrical conductivity of the device substrate is a very important material property for higher frequency operation of RF transistors. The SIT, which is a vertical device, must have a conducting substrate in order to accomodate its backside source contact. The effects of substrate conductivity are much more complicated in MESFET and HEMTs. Substrate conductivity is strongly related to losses at high frequency in microwave MESFETs and HEMTs, since they are lateral devices. At microwave frequencies, the contact pads of the transistor act as lossy transmission lines, and as such create both loss and dispersion in the small-signal characteristics of the device, including smallsignal gain, which is the upper limit of power gain in a transistor. Frequency dispersion of various device elements makes device model extrapolation, wideband device operation, and circuit design all very difficult. Development of semi-insulating SiC substrates of both 6H and 4H polytypes has clearly demonstrated the importance of this material improvement. The device gain in MESFETs on semi-insulating SiC is higher, the substrate losses are smaller, and the dispersion seen in parasitic device elements is decreased as compared to devices on highly doped SiC substrates. Similarly, AlGaN/GaN HFETs fabricated on sapphire (an insulator) or semi-insulating silicon carbide have much better microwave performance than those fabricated on highly doped silicon substrates. This will be discussed in more detail in the device results in the next section. Electrical Contacts Electrical contacts, which are critical to successful device operation, are also strongly influenced by material properties. One of the disadvantages of wide bandgap materials is that they tend to form ohmic contacts with higher contact resistance than ohmic contacts fabricated on smaller bandgap semiconductors. Unfortunately, ohmic contact resitance can strongly influence both DC and RF operation of a device by contributing to the resistive region of the I-V curves shown in Fig. 9.1. As discussed earlier, this increase in the on-resistance adversely affects the extrinsic transconductance, small-signal gain, frequency performance, and power-added efficiency of a device. With optimization, reasonably low contact resistances have been realized in both SiC and GaN n-type materials. High quality Schottky contacts are also critical to successful transistor performance. The quality of its Schottky contact determines the ability of the gate to completely pinch off the device channel, and controls the gate leakage current in the device under both DC and RF conditions. High gate leakage will decrease RF gain and power-added efficiency, and, in turn, the maximum output power of a device. Since good Schottky contacts are typically easy to fabricate on wide bandgap materials, good Schottky gate operation is usually possible in SiC technology. State-of-the-Art Wide Bandgap Microwave Transistor Data The effects of the material properties of wide bandgap semiconductors are best illustrated through the phenomenal device performance being reported today. Despite the immaturity of wide bandgap technology, the DC, small-signal, and large signal results from wide bandgap transistors are already challenging or exceeding the best results reported in many semiconductor material systems. High Frequency Performance ft and fmax are commonly cited for SiC MESFETs, SITs, and AlGaN/GaN HEMTs because they provide an upper limit to the frequencies at which these devices are useful in system applications. Figure 9.6 illustrates both the best performance reported to date for these devices and the performance differences from the device types. The best performance is from the AlGaN/GaN HEMT, with ft = 67 GHz and fmax = 140 GHz [21]. The SiC MESFET is also very fast, with peak ft = 25 GHz and fmax = 50 GHz [22]. The SiC SIT is the weakest performer, with an ft of only 7 GHz [23] and fmax of 8 GHz. The reasons for the differences in performance can be explained through simple device physics. ft is linear with transconductance, which is very high (~240 to 250 mS/mm) for the AlGaN/GaN HEMT. Transconductance in the SiC MESFET is typically on the order of 50 mS/mm, leaving the MESFET with much lower ft. The strong effect of gate capacitance on ft can also be seen with the SiC MESFET. The MESFETs cited with 25 GHz ft are fabricated on semi-insulating substrates. When the same device is fabricated on a conducting SiC substrate, which adds a very large parasitic pad capacitance to both the gate and the drain of the device, the best reported ft drops to about 8 GHz and fmax falls to 16 GHz [24]. Similarly, when an AlGaN/GaN HEMT was fabricated on a highly doped p-type silicon substrate, ft and fmax were both 25 GHz [17]. The SiC SIT has a very large parasitic gate-drain capacitance due to its vertical design, and low transconductance due to the lower doping levels used in this device, so even with careful design and processing, the upper limit of ft for the SIT is expected to be around 20 GHz. fmax is linear with ft, but also depends strongly on gate, source, drain, and channel resistances, output conductance, and gate-drain capacitance. The large differences in fmax among the wide bandgap devices are probably primarily due to the dramatic differences in transconductances in the different devices. This is validated by the fact that the fmax/ft ratio is nearly the same for the AlGaN/GaN HEMT and the SiC MESFET. Power Density Power density, shown in Fig. 9.7, is also an important parameter for evaluation as it is instrumental in determining the minimum device, die, and package size of a microwave transistor. The trend for power density is similar to that of frequency performance. AlGaN/GaN HEMTs have the highest reported power density, 9.1 W/mm at Vds = 30 V [25], due to both the high current density and high breakdown voltage of these devices. SiC MESFETs follow with a significant power density of 5.6 W/mm at Vds = 60 V [26]. While the drain voltage of the MESFET is higher, its current carrying capability (drain current density) is significantly lower than that of the AlGAN/GaN HEMT, and so the power density of the SiC MESFET ends up being lower than that of the AlGaN/GaN HEMT. SiC SITs have lower power density at higher drain voltage, due to their lower current carrying capability. The peak power density for a SiC SIT is 1.3 W/mm at Vds = 90 V [27]. Overall, as seen in Fig. 9.7, the wide bandgap power devices significantly outperform silicon LDMOS and GaAs devices at higher supply voltages. Also worth noting is the fact that the highest power density for an AlGaN/GaN HEMT on a sapphire substrate is only 3.1 W/mm, much less than the 9.1 W/mm reported for a very similar device design on a SiC substrate. This further underscores the importance of substrate thermal conductivity. Total Power Total RF output power, shown in Fig. 9.8, is very important. In the final analysis, it will not matter what power density a transistor achieves if it cannot be scaled up into a total power that is useful for a systemlevel application. In the case of wide bandgap devices, the power requirements for their intended uses (basestations, radar, broadcast, etc.) range from approximately 30 to 1500 W. For total power, the SiC SIT is the device with superior performance. Some of the best reported SIT power data includes a 34.5 cm gate periphery module with 470 W total output power at 600 MHz, and a higher frequency, 3 GHz, 3 cm gate periphery module with 36 W output power and 42% power-added efficiency [27]. The SIT has also been used to make a UHF high power amplifier module designed for HDTV transmission [28]. This module, designed for operation in the 470 to 806 MHz frequency range, had 200 W average output power and 1 kW peak output power. SiC MESFETs have been fabricated with total CW output power of 80 W, and total pulsed output power of 120 W, both at 3.1 GHz [26]. The AlGaN/GaN HEMTs are most limited in total output power at the present time, with the highest reported power of 9.86 W at 8.2 GHz [25]. Also represented in Fig. 9.8 are currently available Si LDMOS parts with output powers as high as 120 W, and GaAs HFETs with 200 W total output power at 2.16 GHz [29] and 15.8 W at 12 GHz [30]. Challenges to Production While there is little doubt that wide bandgap materials have tremendous potential in the high power RF arena, there are still several challenges to production that have yet to be answered. The challenges include the size, defectivity, and choice (SiC/sapphire/silicon) of the device substrate along with the quality and defect density of the epilayers, elimination of dispersion phenomena currently seen in many of these devices, and improved understanding of system packaging and thermal limitations. In addition, market drivers will be needed to provide the impetus for continuing material and device development. It will be very difficult to implement any type of large-scale production of wide bandgap power transistors until these issues are resolved. SiC Substrates SiC substrates have come a long way since they were first introduced over a decade ago. However, they still have a long way to go. The most common "killer" defect in SiC wafers, the micropipe (a screw dislocation that can run the length of a boule of material), has been reduced in density from over 100/cm^2 in 1993 to less than 1/cm2 in 1998 [31]. Those numbers, however, are best research results, and commercially available wafers will have higher micropipe densities, are significantly more expensive than silicon wafers, and are only available in 2″ to 3″ diameters, depending on polytype and doping. The high defect densities in SiC substrates make it difficult to yield large, high voltage, high power devices, while the small wafer sizes increase cost through decreased economy of scale, and can actually be a limiting factor in that it is now difficult to even obtain used semiconductor process equipment for 2″ to 3″ wafers. Substrates for GaN Devices As mentioned earlier, GaN devices have been grown on a number of different substrates. This is because larger diameter (2″) GaN substrates will become available, in prototype quantities only, for the first time in 2000. In the absence of a homoepitaxial GaN wafer, substrate choice for GaN is something of a conundrum. Sapphire is relatively cheap, is offered in large diameter (4″ to 6″) wafers, and provides an excellent low-loss microwave substrate. However, the thermal conductivity of sapphire is extremely poor (0.46 W/cmK) and will severely limit the power density and total power performance of devices fabricated on it. On the other hand, semi-insulating SiC is also an excellent microwave substrate, but has the cost, size, and defectivity issues described above. Silicon is yet another substrate possibility, but there is very limited data as to its performance at this time. Dispersion and Instability Due to Material Defects There have been many reports on both SiC [32] and GaN [33–35] devices of different types of device instabilities and dispersions. Drain current reduction under RF drive and surface instabilities have both been documented for SiC MESFETs. These phenomena have been attribued to traps at both the surface of the device and the buffer/substrate interface. Drain current compression has been widely reported for AlGaN/GaN HEMTs, along with frequency dispersion of transconductance and capacitances. These phenomena in GaN devices have been attributed to hole traps in the buffer layer, traps in the AlGaN barrier, and have even been modeled as a lossy dielectric layer under the gate of the device. In the final analysis, any type of DC-to-RF dispersion is extremely undesirable, not only because of device degradation, but also because is makes circuit design very difficult. Any dispersion effects in devices will have to be eliminated before serious production of wide bandgap devices can occur. System Level Issues There are two system level issues that will need much more study in order to make wide bandgap devices a commercial reality. First, significantly improved packaging will be needed because devices from wide bandgap materials will have much greater power per die and thus power per package than currently available silicon or GaAs devices. Thus, the thermal capabilities of the package for the wide bandgap device will have to be significantly improved over the currently available packaging technology used for silicon power devices. Second, the overall temperature handling and cooling capabilities of the systems using RF power devices will have to be improved. Put simply, there cannot be any advancement in technology if a very high temperature tolerant device operating at a very high temperature and power level causes thermal runaway in the non wide bandgap, temperature-sensitive devices that surround it. Market Drivers One bit of good news for wide bandgap technology is that it appears to be in high demand despite its immature status. Cree Inc. has already announced release of a SiC MESFET product. The U.S. government is providing very large amounts of funding to drive development of wide bandgap technology for military applications [36]. Most importantly, development and sales of blue LEDs from GaN are growing very fast in both demand and level of technology development [37]. The large LED market will drive nitridebased technology to improved materials, which will in turn feed back into microwave device technology, which should in turn mitigate many of the issues described above. MMIC Definition and Concepts Pucel gives an excellent review of Monolithic Microwave Integrated Circuit (MMIC) technology in a 1981 paper. Pucel went on to assemble a collection of papers on the subject in which he states in the introduction: the monolithic approach is an approach wherein all active and passive circuit elements and interconnections are formed, in situ on or within a semi-insulating semi-conductor substrate by a combination of deposition schemes such as epitaxy, ion implantation, sputtering, and evaporation. Figure 10.1 is a conceptual MMIC chip illustrating most of the major components. These include field effect transistor (FET) active devices, metal-insulator-metal (MIM) capacitors, thin film resistors, spiral strip inductors, via hole grounding, and air bridges. As implied by the above quote and Fig. 10.1, in a MMIC all of the circuit components, including transistors, resistors, capacitors, and interconnecting transmission lines are integrated onto a single semiinsulating/ semiconducting (usually GaAs) substrate. Use of a mask set and a corresponding series of processing steps achieves the integrated circuit fabrication. The mask set can be thought of as a mold. Once the mold has been cast, the process can be repeated in a "turn-the-crank" fashion to batch process tens, hundreds, or thousands of essentially identical circuits on each wafer. A Brief History of GaAs MMICs As noted by Pucel, the origin of MMICs may be traced to a 1964 government program at Texas Instruments. A few key milestones are summarized in the following: • 1964 — U.S. government funded a research program at TI based on silicon integrated circuit technology: The objective was a transmit/receive module for a phased array radar antenna. The results were disappointing due to the poor semi-insulating properties of silicon. • 1968 — Mehal and Wacker used semi-insulating gallium arsenide (GaAs) as the substrate with Schottky diodes and Gunn devices as active devices to fabricate an integrated circuit comprising a 94 GHz receiver "front-end." • 1976 — Pengelly and Turner used MESFET devices on GaAs to fabricate an X-band (~10 GHz) amplifier and sparked an intense activity in GaAs MMICs. • 1988 (approximately) — U.S. government's Defense Advanced Research Projects Agency (DARPA, today called ARPA) launched a massive research and development program called the MIMIC program (included Phase I, Phase II, and Phase III efforts) that involved most of the major MMIC manufacturing companies. In the early 1980s a good deal of excitement was generated and several optimistic projections were made predicting the rapid adoption of GaAs MMIC technology by microwave system designers, with correspondingly large profits for MMIC manufacturers. The reality is that there was a much slower rate of progress to widespread use of MMIC technology, with the majority of the early thrust being provided by the government for defense applications. Still, steady progress was made through the 1980s and the government's MIMIC program was very successful in allowing companies to develop lower cost design and fabrication techniques to make commercial application of the technology viable. The 1990s have seen good progress toward commercial use with applications ranging from direct broadcast satellite (DBS) TV receivers, to automotive collision avoidance radar, and the many wireless communication applications (cell phones, WLANs, etc.). Hybrid vs. MMIC Microwave IC Technologies The conventional approach to microwave circuit design that MMIC technology competes with, or is used in combination with, is called "hybrid microwave integrated circuit," "discrete microwave integrated circuit" technology, or simply MIC technology. In a hybrid MIC, the circuit pattern is formed using photolithography. Discrete components are then assembled onto the substrate (e.g., using solder or silver epoxy) and connected using bondwires. In contrast to the batch processing afforded the MMIC approach, MICs have to be assembled with discrete components attached using relatively labor-intensive manufacturing methods. Table 10.1 summarizes some of the contrasting features of hybrid and monolithic approaches. The choice of MMICs vs. the hybrid approach is mainly a matter of volume requirements. The batch processing of MMICs gives this approach advantages for high volume applications. Significant cost savings can be reaped in reduced assembly labor, however, for MMIC the initial design and mask preparation costs are considerable. The cost of maintaining a MMIC manufacturing facility is also extremely high and this has forced several companies out of the business. A couple of examples are Harris, which sold its GaAs operation to Samsung and put its resources into silicon. Another is AT&T, which is also relying on silicon for is anticipated microwave IC needs. The high cost of maintaining a facility can only be offset by high volume production of MMICs. Still this does not prevent companies without MMIC foundries from using the technology, as there are several "commercial foundries" who offset the costs of maintaining their facilities by manufacturing MMIC chip products for third party companies through a foundry design working relationship. A key advantage of MMICs is small size. To give an example, a hybrid MIC the size of a business card can easily be reduced to a small chip one or two millimeters on a side. An associated advantage is the ease of integration that allows several functions to be integrated onto a single chip. For example, Anadigics and Raytheon have both manufactured DBS-related MMICs, wherein the functions of amplification (LNA and IF amplifiers), signal generation (VCO), and signal conversion (mixer) and filtering are all accomplished on a 1 mm × 2 mm, or smaller, chip. In contrast to MMIC, MIC lithography is quite inexpensive and a much smaller scale investment is required to maintain a MIC manufacturing capability. There are also some performance advantages of the hybrid approach. For example, it is much easier to tune or repair a hybrid circuit after fabrication than it is for a MMIC. For this reason, for applications where the lowest noise figure is required, such as in a satellite TV receiver, an individually tuned hybrid LNA may be preferred as the first stage. Ultimately, there is no such thing as a truly all MMIC system. Monolithic technology can be used to integrate single functions, or several system functions, but cannot sustain a system function in isolation. Usually, a MMIC is packaged along with other circuitry to make a practically useful component, or system. Figure 10.2, a radar module made by Raytheon, exemplifies how the advantages of both MMIC and hybrid approaches are realized in a hybrid connection of MMIC chips. Another example of combined hybrid/MMIC technology is shown in Fig. 10.3, in the form of a low noise block downconverter for Direct Broadcast Satellite applications. An example of combined MMIC and hybrid MIC technologies, this radar module includes several MMIC chips interconnected using microstrip lines. The hybrid substrates (white areas) is an alumina insulating substrate; the traces on the hybrid substrate are microstrip lines (courtesy Raytheon Systems Company). GaAs MMICs in Comparison to Silicon VLSI Computer Chips Everyone is familiar with silicon digital IC chips, or at least the enormous impact silicon-based Very Large Scale Integrated (VLSI) circuits have had on the computer industry. Silicon computer chips are digital circuits that contain hundreds to thousands of transistors on each chip. In a digital circuit the transistors are used as switches that are in one of two possible states depending on the "logic" voltage across a pair of terminals. The information processed by a digital circuit consists of a sequence of "1s" and "0s," which translate into logic voltages as the signal passes through the digital IC. Noise distorts the logic waveform in much the same way that it distorts a sinusoidal signal, however, as long as the signal distortion due to noise is not severe, the digital circuitry can assign the correct (discrete) logic levels to the signal as it is processed. Signal interpretation errors that occur due to noise are measured in terms of a bit error rate (BER). The speed of the digital processing is related to how fast the transistors can switch between one state and another, among other factors. Because of certain material factors, such as electron mobility, digital circuits made on GaAs have been demonstrated to have speed advantages over silicon digital ICs, however, the speed advantages have not been considered by the majority of companies to outweigh the significant economic advantages of well-established, lower cost, silicon processing technology. Because of the large volume of silicon chips that have been produced over the last twenty years, silicon processing techniques are significantly more established and in many cases standardized as compared to GaAs processing techniques, which still vary widely from foundry to foundry. The digital nature of the signals and operation modes of transistors in digital ICs makes uniformity between digital ICs, and even similar ICs made by different manufacturers, much easier to achieve than achieving uniformity with analog GaAs MMICs. In contrast, GaAs MMICs are analog circuits that usually contain less than 10 transistors on a typical chip. The analog signals processed, which can take on any value between certain limits, may generally be thought of as combinations of noisy sinusoidal signals. Bias voltages are applied to the transistors in such a way that each transistor will respond in one of several predetermined ways to an applied input signal. One common use for microwave transistors is amplification, whereby the result of a signal passing through the transistor is for it to be boosted by an amount determined by the gain of the transistor. A complication that arises is that no two transistors are identical in the analog sense. Taking gain for example, while there will be a statistical distribution of gain for a set of amplifier chips measured on the same GaAs MMIC wafer, a different (wider) set of statistics applies to variations in gain from wafer-to-wafer for the same design. These variations are caused primarily by variations in transistors, but also by variations in other components that make up the MMIC, including MIM capacitors, spiral inductors, film resistors, and transmission line interconnects. Successful foundries are able to control the variations within acceptable limits in order to achieve a satisfactory yield of chips meeting a customer's requirements. However, translating a MMIC design mask set to a different manufacturing foundry is a different story altogether. This is not to say that foundry translation of MMIC designs cannot be accomplished. Under the federally funded MIMIC program, mentioned earlier, several pairs of foundries were tasked to translate designs from one to the other to demonstrate a "second-sourcing" capability. These efforts met with varying degrees of success, but not without considerable effort on the part of the participating GaAs MMIC foundries. Two pairs of companies involved in this second-sourcing demonstration effort for the MIMIC program are Raytheon and Texas Instruments, and Hughes Aircraft Company (GaAs foundry since bought and closed by Raytheon Company) and General Electric Company (now part of Lockheed-Martin). MMIC Yield and Cost Considerations Yield is an important concept for MMICs and refers to the percentage of circuits on a given wafer with acceptable performance relative to the total number of circuits fabricated. Since yield may be defined at several points in the MMIC process, it must be interpreted carefully. • DC yield is the number of circuits whose voltages and currents measured at DC are within acceptable limits. • RF yield is generally defined as the number of circuits that have acceptable RF/microwave performance when measured "on-wafer," before circuit dicing. • Packaged RF yield is the final determination of the number of acceptable MMIC products that have been assembled using the fabricated MMIC chips. If measured in terms of the total number of circuits fabricated, each of these yields will be successively lower numbers. For typical foundries, DC yields exceed 90%, while packaged yields may be around 50%. Final packaged RF yield depends heavily on the difficulty of the RF specifications, the uniformity of the process (achieved by statistical process control), as well as how sensitive the RF performance of the circuit design is to fabrication variations. The costs involved with MMICs include: • Material • Design • Mask set preparation • Wafer processing • Capital equipment • Testing • Packaging • Inspection A typical wafer run may cost $20,000 to $50,000, with $5,000 to $10,000 attributable to the mask set alone. These figures do not include design costs. Per-chip MMIC costs are determined by: • Difficulty of design specifications • Yield • Material (wafer size and quality) • Production volume • Degree of automation Some 1989–90 example prices for MMIC chips are as follows: 1 to 5 GHz Wideband Amplifier — $30.00 2 to 8 GHz Wideband Amplifier — $45.00 6 to 18 GHz Wideband Amplifier — $100.00 DC to 12 GHz Attenuator — $60.00 DBS downconverter chip — $10.00. In comparison, example prices for 1999 MMIC chips are as follows: DBS Downconverter chip — <$2.50 DC to 8 GHz HBT MMIC amp. — ~$3 Packaged power FET MMIC — $1 for ~2 GHz 4 to 7 GHz and 8 to 11 GHz high power/high efficiency power amps. — $85 (2 Watt) to $330 (12 Watt) Prices for low volume specials at high frequency have not moved much since 1989. Si vs. GaAs for Microwave Integrated Circuits The subject of Silicon versus GaAs has been a hotly debated subject since the beginning of the MMIC concept in around 1965 (see "A brief history of GaAs MMICs" above). Two of the main discriminating issues between the technologies are microwave transistor performance and the loss of the semiconductor when used as a semi-insulating substrate for passive components. A comparison of relevant physical parameters for silicon and GaAs materials is given in Table 10.2. The dielectric constants of the materials mainly affects the velocity of propagation down transmission line interconnects, and for the materials compared, this parameter is on the same order. For the other factors considered, significant differences are observed. The thermal conductivity, a measure of how efficiently the substrate conducts heat (generated by DC currents) away from the transistors, is best for silicon and is one key advantage of the silicon approach. This advantage is offset by silicon's lower mobility and lower resistivity. Mobility in a semiconductor is a measure of how easily electrons can move through the "doped" region of the semiconductor (see discussion of FET operation in the following section). The mobility, as well as the saturated velocity, have a strong influence on the maximum frequency at which a microwave transistor can have useful gain. Turning our attention to passive component operation, GaAs has much better properties for lower loss passive circuit realization. With the exception of a resistor, the ideal passive component is a transmission line, inductor, or capacitor that causes no signal loss. Resistivity is a measure of how "resistant" the substrate is to leakage currents that could flow, for example, from the top conductor of a microstrip line and the ground plane below. Looking first at the properties of the insulators sapphire and alumina, the resistivity is seen to be quite high. Semi-insulating GaAs is almost as high, and silicon has the lowest resistivity (highest leakage currents for a given voltage). These considerations have led many companies to invest heavily in GaAs technology for microwave applications over the last several years. However, silicon remains a strong contender. In fact there has been a very strong renewal in development of silicon MMICs with the advent of numerous markets for microwave "wireless" products. The front lines of the battlefield between silicon and GaAs are at frequencies below 6 GHz, where potential commercial opportunities are numerous. Silicon-based microwave ICs are also beginning to appear in higher frequency applications, such as Ku-band DBS satellite receivers. Silicon-germanium heterojunction bipolar transistor technology is paving the way for increasing the applicability of silicon technology to even higher frequencies. Basic Principles of GaAs MESFETs and HEMTs Basic MESFET Structure The primary active device in a GaAs MMIC is the metal electrode semiconductor field-effect transistor, or MESFET. The basic construction of a MESFET is shown in Figs. 10.4 and 10.5. An "active layer" is first formed on top of a semi-insulating GaAs substrate by intentionally introducing an n-type impurity onto the surface of the GaAs, and isolating specific channel regions. These channel regions are semiconducting in that they contain free electrons that are available for current flow. When a metal is placed in direct contact with a semiconductor, as in the case of the gate, a "Schottky diode" is formed. One of the consequences of this is that a natural "depletion region," a region depleted of available electrons is formed under the gate. A diode allows current flow easily in one direction, while impeding current flow in the other direction. In the case of a MESFET gate, a positive bias voltage between the gate and the source "turns on" the diode and allows current to flow between the gate and the source through the substrate. A negative bias between the gate and the drain "turns off" the diode and blocks current flow, it also increases the depth of the depletion region under the gate. In contrast to the gate contact, the drain and source contacts are made using what are called "ohmic contacts." In an ohmic contact, current can flow freely in both directions. Whether an ohmic contact or Schottky diode is formed at the metal-semiconductor interface is determined by the composition of the metal placed on the interface and the doping of the semiconductor region directly under the metal. The introduction of "pocket n+ implants" help form the ohmic contacts in the FET structure illustrated in Fig. 10.4. In the absence of the gate, the structure formed by the active channel in combination with the drain and source contacts essentially behaves as a resistor obeying ohms law. In fact this is exactly how one type of GaAs-based resistor commonly used in MMICs is made. FETs in Microwave Applications The most common way to operate a MESFET, for example in an amplifier application, is to ground the source (also called "common source" mode), introduce a positive bias voltage between the drain and source, and a negative bias voltage between the gate and source. The positive voltage between the drain and source Vds causes current Ids to flow in the channel. As negative bias is applied between the gate and source Vgs the current Ids is reduced as the depletion region extends farther and farther into the channel region. The value of current that flows with zero gate-to-source voltage is called the saturation current Idss. Eventually, at a sufficiently large negative voltage, the channel is completely depleted of free electrons and the current Ids will be reduced to essentially zero. This condition is called "pinch off." In most amplifier applications, the negative gate voltage is set to a "bias condition" between 0 volts and the pinch-off voltage Vpo. Figure 10.6 gives a simplified view of a FET configured in an amplifier application. An input sinusoidal signal Vgs(t) is shown offset by a negative DC bias voltage. The sinusoidal variation in Vgs causes a likewise sinusoidal variation in depth of the depletion region that in turn creates a sinusoidal variation (or modulation) in the output current. Amplification occurs because small variations in the Vgs voltage cause relatively large variations in the output current. By passing the output current through a resistance RL the voltage waveform Vds(t) is formed. The Vds waveform is shown to have higher amplitude than Vgs to illustrate the amplification process. Other common uses, which involve different configurations and biasing arrangements, include use of FETs as the basis for mixers and oscillators (or VCOs). FET Fabrication Variations and Layout Approaches Figure 10.7 illustrates a MESFET fabricated with a recessed gate, along with a related type of FET device called a high electron mobility transistor (HEMT). A recessed gate is used for a number of reasons. First in processing it can aid in assuring that the gate stripe is placed in the proper position between the drain and source, and it can also result in better control and uniformity in Idss and Vpo. A HEMT is a variation of the MESFET structure that generally produces a higher performing device. This translates, for example, into a higher gain and a lower noise figure at a given frequency. In light of the above cursory understanding of microwave FET structures, some qualitative comments can be made about some of the main factors that cause intended and unintended variations in FET performance. The first factor is the doping profile in the active layer. The doping profile refers to the density of the charge carriers (i.e., electrons) as a function of depth into the substrate. For the simplest type, uniform doping, the density of dopants (intended impurities introduced in the active region) is the same throughout the active region. In practice, there is a natural "tail" of the doping profile that refers to a gradual decrease in doping density as the interface between the active layer and the semiinsulating substrate is approached. One approach to create a more abrupt junction is the so-called "buried P-layer" technique. The buried p-layer influences the distribution of electrons versus depth from the surface of the chip in the "active area" of the chip where the FET devices are made. The idea is create better definition between where the conducting channel stops and where the nonconducting substrate begins. (More specifically the buried p-layer counteracts the n-type dopants in the tail of the doping profile.) The doping profile and density determine the number of charge carriers available for current flow in a given cross-section of the active channel. This has a strong influence on the saturation current Idss and pinch-off voltage Vpo. The depth of the active layer (dimension "a" of Fig. 10.5) also plays a critical role in determining the current characteristics. Other variables that influence MESFET performance are the gate length and gate width ("L" and "Z" of Fig. 10.5). The names for these two parameters are counterintuitive since the gate length refers to the shorter of the two dimensions. The gate width and channel depth determine the cross-sectional area available for current flow. An increase in gate width increases the value of the saturation current, which translates into the ability to operate the device at higher RF power levels (or AC voltage amplitudes). Typical values for gate widths are in the range of 100 microns for low noise devices to over 10 millimeters for high power devices. The gate length is usually the minimum feature size of a device and is the most significant factor in determining the maximum frequency where useful gain can be obtained from a FET; generally, the smaller the gate length the higher the gain for a given frequency. However, the fabrication difficulty increases, and processing yield decreases, as the gate length is reduced. The difficulty arises from the intricacy in controlling the exact position and length (small dimension) of the gate. The geometrical layout of the FET also influences performance. Figure 10.8 shows common FET layouts. The layout affects what are called "external parasitics," which are undesired effects that can be modeled as a combination of capacitors, inductors, and resistors added to the basic FET electrical model. In MMIC fabrication, variations in the most of the above-mentioned parameters are a natural consequence of a real process. These variations cause variations in observed FET performance even for identical microwave FETs made using the same layout geometry on the same wafer. Certainly there are many more subtle factors that influence performance, but the factors considered here should give some intuitive understanding of how unavoidable variations in the physical structure of fabricated FETs cause variations in microwave performance. As previously mentioned, successful GaAs MMIC foundries use statistical process control methods to produce FET devices within acceptable limits of uniformity between devices. MMIC Lumped Elements: Resistors, Capacitors, and Inductors MMIC Resistors Figure 10.9 shows three common resistor types used in GaAs MMICs. For MMIC resistors the type of resistor material, and the length and width of the resistor determine the value of the resistance. In practice, there are also unwanted "parasitic" effects associated with MMIC resistors that can be modeled generally as a combination of series inductance, and capacitance to ground in addition to the basic resistance of the component. MMIC Capacitors The most commonly used type of MMIC capacitor is the metal-insulator-metal capacitor shown in Fig. 10.10. In a MIM capacitor the value of capacitance is determined from the area of the overlapping metal (smaller dimension of two overlapping plates), the dielectric constant εr of the insulator material, typically silicon nitride, and the thickness of the insulator. For values less than about 0.2 pF, series connected MIM capacitors can be used. Smaller values of capacitance can be achieved with one of the various arrangements of coupled lines illustrated in Fig. 10.11. For these capacitors, the capacitance is determined from the width and spacing of strips on the surface of the wafer. At microwave frequencies, "parasitic" effects limit the performance of all these capacitors. The two main effects are signal loss due to leakage currents, as measured by the quality factor Q of the capacitor, and a self-resonance frequency, beyond which the component no longer behaves as a capacitor. The final wafer or chip thickness can have a strong influence on these parasitic effects and the associated performance of the capacitors in the circuit. Parasitic effects must be accurately modeled for successful MMIC design usage. MMIC Inductors MMIC inductors are realized with narrow strips of metal on the surface of the chip. Various layout geometries are possible as illustrated in Fig. 10.12(a). The choice of layout is dictated mainly by the available space and the amount of inductance L that is required in the circuit application, with the spiral inductors providing the highest values. The nominal value of inductance achievable from strip inductors is determined from the total length, for the simpler layouts, and by the number of turns, spacing, and line width for the spiral inductors. At microwave frequencies, "parasitic" effects limit the performance of these inductors. The two main effects are signal loss due to leakage currents, as measured by the quality factor Q of the capacitor, and a self-resonance frequency, beyond which the component no longer behaves as an inductor. The final thickness of the substrate influences not only the nominal value of inductance, but also the quality factor and self-resonance frequency. Inductor parasitic effects must be accurately modeled for successful MMIC design usage. Air Bridge Spiral Inductors Air bridge spiral inductors are distinguished from conventional spiral inductors by having the metal traces that make up the inductor suspended from the top of the substrate using MMIC air bridge technology. MMIC air bridges are generally used to allow crossing lines to jump over one another without touching and are almost invariably used in conventional spiral inductors to allow the center of the spiral to be brought through the turns of the spiral inductor for connection to the circuit outside of the spiral. In an air bridge spiral inductor, all of the turns are suspended off the substrate using a series of air bridges supported by metalized posts. The reason for doing this is to improve inductor performance by reducing loss as well as the effective dielectric constant of the lines that make up the spiral. The latter can have the effect of reducing inter-turn capacitance and increasing the resonant frequency of the inductor. Whether or not air bridge inductors are "worth the effort" is a debatable subject as the air bridge process is an important yield-limiting factor. This means circuit failure due to collapsed air bridges, for example, occur at an increasing rate, the more air bridges that are used. Typical Values for MMIC Lumped Elements Each MMIC fabrication foundry sets its limits on the geometrical dimensions and range of materials available to the designer in constructing the MMIC lumped elements MMIC Processing and Mask Sets The most common MMIC process approach in the industry can be characterized as having 0.5 micron gate length MESFETs fabricated on a GaAs wafer whose final thickness is 100 microns, or 4 mils. The back side of the wafer has plated gold; via holes are used to connect from the back side of the wafer to the topside of the wafer. Although specific procedures and steps vary from foundry to foundry, Fig. 10.12b illustrates a typical process fuente: rf and microwave semiconductor device handbook. mike golio
BJT under normal operation, wherein the baseemitter bias (VBE) is positive and the base-collector bias (VBC) is negative. The bipolar transistor was detailed in the previous chapter. Here we use Fig. 5.2 to emphasize that the energy gap is the same throughout the entire transistor structure. The Fermi levels and the depletion regions of the band diagram reflect the BJT design constraint that the doping level is highest in the emitter, and lowest in the collector. The Fermi level in the emitter is above the conduction band, signifying that the emitter is degenerately doped. A BJT has two key current components. The first is the forward-injection current conducted by the electrons. These electrons are emitted at the emitter, crossing the base-emitter potential barrier with the
help of the VBE bias, diffusing through the thin base layer as minority carriers, and then are swept by the large electric field in the reverse-biased base-collector junction. The carriers finally leave the collector, forming the collector current (IC). In their journey, only a few electrons are lost through recombinations with the majority holes in the base. We therefore denote the electron current as IC in Fig. 5.2, even though the current magnitude in the emitter is slightly larger than that which finally exits the collector terminal. Of the three phases of the journey, the diffusion through the base layer is the rate-limiting step. Hence, a quantitative expression of IC, to be developed shortly, relates intimately to the base layer parameters. By varying VBE , we control the amount of the electron injection from the emitter to the base, and subsequently, the amount of electrons collected at the collector. This current flow, however, is independent of VBC, as long as the base-collector junction is reverse biased. The property that the desired signal (IC) is modified by the input bias (VBE) but unaffected by the output bias (VBC) fulfills the requirement of a
Navega con el navegador más seguro de todos. ¡Descárgatelo ya!
No hay comentarios:
Publicar un comentario